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diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 26bd11f95fa7b3ee6718e1f18f2a0179828c1a7b..1d71a0164be2a5f40766d82fff9a14997b62a07d 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -923,22 +923,22 @@ TODO generate table which will be here [[svp64/reg_profiles]]
 
 ### Single-predicated Instruction
 
-illustration of normal mode add operation: zeroing not included, elwidth overrides not included.
+illustration of normal mode add operation: zeroing not included, elwidth overrides not included.  if there is no predicate, it is set to all 1s
 
     function op_add(rd, rs1, rs2) # add not VADD!
       int i, id=0, irs1=0, irs2=0;
       predval = get_pred_val(FALSE, rd);
-      rd  = int_vec[rd ].isvector ? int_vec[rd ].regidx : rd;
-      rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
-      rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
+      rd  = int_vec[rd ].isvec ? int_vec[rd ].regidx : rd
+      rs1 = int_vec[rs1].isvec ? int_vec[rs1].regidx : rs1
+      rs2 = int_vec[rs2].isvec ? int_vec[rs2].regidx : rs2
       for (i = 0; i < VL; i++)
         STATE.srcoffs = i # save context
         if (predval & 1<<i) # predication uses intregs
            ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
-           if (!int_vec[rd ].isvector) break;
-        if (int_vec[rd ].isvector)  { id += 1; }
-        if (int_vec[rs1].isvector)  { irs1 += 1; }
-        if (int_vec[rs2].isvector)  { irs2 += 1; }
+           if (!int_vec[rd ].isvec) break;
+        if (int_vec[rd ].isvec)  { id += 1; }
+        if (int_vec[rs1].isvec)  { irs1 += 1; }
+        if (int_vec[rs2].isvec)  { irs2 += 1; }
         if (id == VL or irs1 == VL or irs2 == VL) {
           # end VL hardware loop
           STATE.srcoffs = 0; # reset