Move dffinit til after abc

diff --git a/techlibs/xilinx/.synth_xilinx.cc.swn b/techlibs/xilinx/.synth_xilinx.cc.swn
deleted file mode 100644 (file)
index a656469..0000000
Binary files a/techlibs/xilinx/.synth_xilinx.cc.swn and /dev/null differ

diff --git a/techlibs/xilinx/.synth_xilinx.cc.swo b/techlibs/xilinx/.synth_xilinx.cc.swo
deleted file mode 100644 (file)
index 6fc27ed..0000000
Binary files a/techlibs/xilinx/.synth_xilinx.cc.swo and /dev/null differ

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ee8dec9eec2cf37e449123ced07536675222da0c..2676f59157851b6b240d743e995b1c81e1ffd84e 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -284,8 +284,6 @@ struct SynthXilinxPass : public Pass
                if (check_label(active, run_from, run_to, "map_cells"))
                {
                        Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v");
-                       Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-                                       "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
                        Pass::call(design, "clean");
                }
 
@@ -295,6 +293,8 @@ struct SynthXilinxPass : public Pass
                        Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
                        Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
+                       Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+                                       "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
                }
 
                if (check_label(active, run_from, run_to, "check"))