fhdl/verilog: add reserved keywords

diff --git a/migen/fhdl/namer.py b/migen/fhdl/namer.py
index e0b14fc88c24093b1e641da818e996065973429a..9044aa86f29af8ad1ae4b0bd8a37f0740d1603df 100644 (file)
--- a/migen/fhdl/namer.py
+++ b/migen/fhdl/namer.py
@@ -212,9 +212,9 @@ def _build_pnd(signals):
     return pnd
 
 
-def build_namespace(signals):
+def build_namespace(signals, reserved_keywords=set()):
     pnd = _build_pnd(signals)
-    ns = Namespace(pnd)
+    ns = Namespace(pnd, reserved_keywords)
     # register signals with name_override
     for signal in signals:
         if signal.name_override is not None:
@@ -223,8 +223,8 @@ def build_namespace(signals):
 
 
 class Namespace:
-    def __init__(self, pnd):
-        self.counts = {}
+    def __init__(self, pnd, reserved_keywords=set()):
+        self.counts = {k: 1 for k in reserved_keywords}
         self.sigs = {}
         self.pnd = pnd
 

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index b81e0e716340445b1ae5cee9fd6355019d73d5db..39d87d75fc55ecc961ea5ee34e07f241e975a2b9 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -8,6 +8,26 @@ from migen.fhdl.bitcontainer import bits_for, flen
 from migen.fhdl.namer import Namespace, build_namespace
 from migen.fhdl.conv_output import ConvOutput
 
+_reserved_keywords = {
+"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
+"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
+"defparam", "design", "disable", "edge", "else", "end", "endcase", "endconfig",
+"endfunction", "endgenerate", "endmodule", "endprimitive", "endspecify",
+"endtable", "endtask", "event", "for", "force", "forever", "fork", "function",
+"generate", "genvar", "highz0", "highz1", "if", "ifnone", "incdir", "include",
+"initial", "inout", "input", "instance", "integer", "join", "large", "liblist",
+"library", "localparam", "macromodule", "medium", "module", "nand", "negedge",
+"nmos", "nor", "noshowcancelled", "not", "notif0", "notif1", "or", "output",
+"parameter", "pmos", "posedge", "primitive", "pull0", "pull1" "pulldown"
+"pullup","pulsestyle_onevent", "pulsestyle_ondetect", "remos", "real",
+"realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran", "rtranif0",
+"rtranif1", "scalared", "showcancelled", "signed", "small", "specify",
+"specparam", "strong0", "strong1", "supply0", "supply1", "table", "task",
+"time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand",
+"trior", "trireg", "unsigned", "use", "vectored", "wait", "wand", "weak0",
+"weak1", "while", "wire", "wor","xnor","xor"}
+
+
 def _printsig(ns, s):
     if s.signed:
         n = "signed "
@@ -324,7 +344,7 @@ def convert(f, ios=None, name="top",
 
     ns = build_namespace(list_signals(f) \
         | list_special_ios(f, True, True, True) \
-        | ios)
+        | ios, _reserved_keywords)
     r.ns = ns
 
     src = "/* Machine-generated using Migen */\n"