int
fs_visitor::virtual_grf_alloc(int size)
{
- if (virtual_grf_array_size <= virtual_grf_next) {
+ if (virtual_grf_array_size <= virtual_grf_count) {
if (virtual_grf_array_size == 0)
virtual_grf_array_size = 16;
else
virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int,
virtual_grf_array_size);
}
- virtual_grf_sizes[virtual_grf_next] = size;
- return virtual_grf_next++;
+ virtual_grf_sizes[virtual_grf_count] = size;
+ return virtual_grf_count++;
}
/** Fixed HW reg constructor. */
void
fs_visitor::split_virtual_grfs()
{
- int num_vars = this->virtual_grf_next;
+ int num_vars = this->virtual_grf_count;
bool split_grf[num_vars];
int new_virtual_grf[num_vars];
if (0) {
/* Debug of register spilling: Go spill everything. */
- int virtual_grf_count = virtual_grf_next;
for (int i = 0; i < virtual_grf_count; i++) {
spill_reg(i);
}
void
fs_visitor::assign_regs_trivial()
{
- int hw_reg_mapping[this->virtual_grf_next + 1];
+ int hw_reg_mapping[this->virtual_grf_count + 1];
int i;
int reg_width = c->dispatch_width / 8;
/* Note that compressed instructions require alignment to 2 registers. */
hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
- for (i = 1; i <= this->virtual_grf_next; i++) {
+ for (i = 1; i <= this->virtual_grf_count; i++) {
hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
this->virtual_grf_sizes[i - 1] * reg_width);
}
- this->grf_used = hw_reg_mapping[this->virtual_grf_next];
+ this->grf_used = hw_reg_mapping[this->virtual_grf_count];
foreach_list(node, &this->instructions) {
fs_inst *inst = (fs_inst *)node;
* for reg_width == 2.
*/
int reg_width = c->dispatch_width / 8;
- int hw_reg_mapping[this->virtual_grf_next];
+ int hw_reg_mapping[this->virtual_grf_count];
int first_assigned_grf = ALIGN(this->first_non_payload_grf, reg_width);
int base_reg_count = (max_grf - first_assigned_grf) / reg_width;
int class_sizes[base_reg_count];
*/
class_sizes[class_count++] = 2;
}
- for (int r = 0; r < this->virtual_grf_next; r++) {
+ for (int r = 0; r < this->virtual_grf_count; r++) {
int i;
for (i = 0; i < class_count; i++) {
reg_width, base_reg_count);
struct ra_graph *g = ra_alloc_interference_graph(brw->wm.regs,
- this->virtual_grf_next);
+ this->virtual_grf_count);
- for (int i = 0; i < this->virtual_grf_next; i++) {
+ for (int i = 0; i < this->virtual_grf_count; i++) {
for (int c = 0; c < class_count; c++) {
if (class_sizes[c] == this->virtual_grf_sizes[i]) {
/* Special case: on pre-GEN6 hardware that supports PLN, the
* numbers.
*/
this->grf_used = first_assigned_grf;
- for (int i = 0; i < this->virtual_grf_next; i++) {
+ for (int i = 0; i < this->virtual_grf_count; i++) {
int reg = ra_get_node_reg(g, i);
hw_reg_mapping[i] = (first_assigned_grf +
fs_visitor::choose_spill_reg(struct ra_graph *g)
{
float loop_scale = 1.0;
- float spill_costs[this->virtual_grf_next];
- bool no_spill[this->virtual_grf_next];
+ float spill_costs[this->virtual_grf_count];
+ bool no_spill[this->virtual_grf_count];
- for (int i = 0; i < this->virtual_grf_next; i++) {
+ for (int i = 0; i < this->virtual_grf_count; i++) {
spill_costs[i] = 0.0;
no_spill[i] = false;
}
}
}
- for (int i = 0; i < this->virtual_grf_next; i++) {
+ for (int i = 0; i < this->virtual_grf_count; i++) {
if (!no_spill[i])
ra_set_node_spill_cost(g, i, spill_costs[i]);
}