Fix .force_thumb

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f08fd6895a2624be1327adb716f3412f9c08d441..384aae8c7e854a2ea6891fd1900fdeb01ca1788c 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+1999-11-29  Nick Clifton  <nickc@cygnus.com>
+
+       * config/tc-arm.c (thumb_mode): Turn into a tristate variable.
+       (s_force_thumb): Set thumb_mode to 2.
+       (md_assemble): Do not complain about thumb instructions on a
+       non-thumb target if thumb_mode is set to 2.
+
 1999-11-28  Michael Meissner  <meissner@cygnus.com>
 
        * config/tc-alpha.c (toplevel): Include struc-symbol.h.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index fa61988aa40a241920fda982d91f5a7d749a497d..c6e241699b64bc1ea10ad85ddb601b3783cc59af 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -139,10 +139,11 @@ CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
 symbolS * GOT_symbol;          /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
 #endif
 
-CONST int md_reloc_size = 8;           /* Size of relocation record */
-
-static int thumb_mode = 0;      /* non-zero if assembling thumb instructions */
+CONST int md_reloc_size = 8;   /* Size of relocation record */
 
+static int thumb_mode = 0;      /* 0: assemble for ARM, 1: assemble for Thumb,
+                                  2: assemble for Thumb even though target cpu
+                                  does not support thumb instructions */
 typedef struct arm_fix
 {
   int thumb_mode;
@@ -1260,7 +1261,7 @@ s_force_thumb (ignore)
      
   if (! thumb_mode)
     {
-      thumb_mode = 1;
+      thumb_mode = 2;
       
       record_alignment (now_seg, 1);
     }
@@ -6068,7 +6069,7 @@ md_assemble (str)
       if (opcode)
        {
          /* Check that this instruction is supported for this CPU.  */
-         if ((opcode->variants & cpu_variant) == 0)
+         if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
             {
                as_bad (_("selected processor does not support this opcode"));
                return;