freedreno/a6xx: Implement PrimID passthrough
authorConnor Abbott <cwabbott0@gmail.com>
Thu, 23 Apr 2020 09:56:07 +0000 (11:56 +0200)
committerMarge Bot <eric+marge@anholt.net>
Sat, 25 Apr 2020 01:06:21 +0000 (01:06 +0000)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>

src/gallium/drivers/freedreno/a6xx/fd6_emit.c
src/gallium/drivers/freedreno/a6xx/fd6_program.c

index 59c2d15a266ee605f01b47e990cb2fcc8094d6a9..9295175404dfdabc69653c702cfbbef480cc42c9 100644 (file)
@@ -1302,7 +1302,6 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
 
        WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 
-       WRITE(REG_A6XX_PC_PRIMID_CNTL, 0);
        WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
        WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
 
index 9e12cb246c9314937fd896ec8ec40031f31fff51..6e19deee03ef8cd8ae813378ab93fe668c56fffd 100644 (file)
@@ -431,6 +431,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
        const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
        ir3_link_shaders(&l, last_shader, fs, true);
 
+       bool primid_passthru = l.primid_loc != 0xff;
+
        OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
        OUT_RING(ring, ~l.varmask[0]);  /* VPC_VAR[0].DISABLE */
        OUT_RING(ring, ~l.varmask[1]);  /* VPC_VAR[1].DISABLE */
@@ -590,7 +592,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
        OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
        OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
                         COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
-                        0xff00ff00);
+                        A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
+                        A6XX_VPC_CNTL_0_UNKLOC(0xff));
 
        OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
        OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
@@ -786,6 +789,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
        if (fs->instrlen)
                fd6_emit_shader(ring, fs);
 
+       OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
+       OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
+
        OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
        OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
                        A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
@@ -800,7 +806,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
        OUT_RING(ring, 0x000000fc);   /* VFD_CONTROL_4 */
        OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
                        0xfc00);   /* VFD_CONTROL_5 */
-       OUT_RING(ring, 0x00000000);   /* VFD_CONTROL_6 */
+       OUT_RING(ring,
+                        COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU));   /* VFD_CONTROL_6 */
 
        bool fragz = fs->no_earlyz | fs->writes_pos;