const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
ir3_link_shaders(&l, last_shader, fs, true);
+ bool primid_passthru = l.primid_loc != 0xff;
+
OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
- 0xff00ff00);
+ A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
+ A6XX_VPC_CNTL_0_UNKLOC(0xff));
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
if (fs->instrlen)
fd6_emit_shader(ring, fs);
+ OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
+ OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
+
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
0xfc00); /* VFD_CONTROL_5 */
- OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
+ OUT_RING(ring,
+ COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
bool fragz = fs->no_earlyz | fs->writes_pos;