Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 81269f094834f43b4e908321bfce2e031b39d2a4

diff --combined src/cpu/o3/lsq_unit.hh
index ebfa750597f3cdce7dc5f672eb44d440447fdd2b,e1b27048dd9a4d8a61ae273ca31d1438788eaafa..f24de20d9b1f408593fc90c4a8d8008025f57100
--- 1/src/cpu/o3/lsq_unit.hh
--- 2/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@@ -73,8 -73,8 +73,8 @@@ class LSQUnit 
      LSQUnit();
  
      /** Initializes the LSQ unit with the specified number of entries. */
-     void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
-               unsigned maxSQEntries, unsigned id);
+     void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
+               unsigned maxLQEntries, unsigned maxSQEntries, unsigned id);
  
      /** Returns the name of the LSQ unit. */
      std::string name() const;
@@@ -82,16 -82,8 +82,8 @@@
      /** Registers statistics. */
      void regStats();
  
-     /** Sets the CPU pointer. */
-     void setCPU(O3CPU *cpu_ptr);
- 
-     /** Sets the IEW stage pointer. */
-     void setIEW(IEW *iew_ptr)
-     { iewStage = iew_ptr; }
- 
      /** Sets the pointer to the dcache port. */
-     void setDcachePort(Port *dcache_port)
-     { dcachePort = dcache_port; }
+     void setDcachePort(Port *dcache_port);
  
      /** Switches out LSQ unit. */
      void switchOut();
@@@ -297,19 -289,15 +289,19 @@@
      struct SQEntry {
          /** Constructs an empty store queue entry. */
          SQEntry()
 -            : inst(NULL), req(NULL), size(0), data(0),
 +            : inst(NULL), req(NULL), size(0),
                canWB(0), committed(0), completed(0)
 -        { }
 +        {
 +            bzero(data, sizeof(data));
 +        }
  
          /** Constructs a store queue entry for a given instruction. */
          SQEntry(DynInstPtr &_inst)
 -            : inst(_inst), req(NULL), size(0), data(0),
 +            : inst(_inst), req(NULL), size(0),
                canWB(0), committed(0), completed(0)
 -        { }
 +        {
 +            bzero(data, sizeof(data));
 +        }
  
          /** The store instruction. */
          DynInstPtr inst;
@@@ -318,7 -306,7 +310,7 @@@
          /** The size of the store. */
          int size;
          /** The store data. */
 -        IntReg data;
 +        char data[sizeof(IntReg)];
          /** Whether or not the store can writeback. */
          bool canWB;
          /** Whether or not the store is committed. */
@@@ -566,14 -554,22 +558,14 @@@ LSQUnit<Impl>::read(Request *req, T &da
          if ((store_has_lower_limit && store_has_upper_limit)) {
              // Get shift amount for offset into the store's data.
              int shift_amt = req->getVaddr() & (store_size - 1);
 -            // @todo: Magic number, assumes byte addressing
 -            shift_amt = shift_amt << 3;
 -
 -            // Cast this to type T?
 -            data = storeQueue[store_idx].data >> shift_amt;
  
 -            // When the data comes from the store queue entry, it's in host
 -            // order. When it gets sent to the load, it needs to be in guest
 -            // order so when the load converts it again, it ends up back
 -            // in host order like the inst expects.
 -            data = TheISA::htog(data);
 +            memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
  
              assert(!load_inst->memData);
              load_inst->memData = new uint8_t[64];
  
 -            memcpy(load_inst->memData, &data, req->getSize());
 +            memcpy(load_inst->memData,
 +                    storeQueue[store_idx].data + shift_amt, req->getSize());
  
              DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
                      "addr %#x, data %#x\n",
@@@ -720,10 -716,7 +712,10 @@@ LSQUnit<Impl>::write(Request *req, T &d
  
      storeQueue[store_idx].req = req;
      storeQueue[store_idx].size = sizeof(T);
 -    storeQueue[store_idx].data = data;
 +    assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
 +
 +    T gData = htog(data);
 +    memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
  
      // This function only writes the data to the store queue, so no fault
      // can happen here.

diff --combined src/cpu/o3/lsq_unit_impl.hh
index a47528e32d2489a96ac6d173b8637e865e4db6d8,2aa0d6b6a66a6c8359d45df840c897d42f996d61..d558e2dfa5129a51418c4f0e514989993e643927
--- 1/src/cpu/o3/lsq_unit_impl.hh
--- 2/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@@ -57,6 -57,11 +57,11 @@@ LSQUnit<Impl>::WritebackEvent::process(
      if (!lsqPtr->isSwitchedOut()) {
          lsqPtr->writeback(inst, pkt);
      }
+ 
+     if (pkt->senderState)
+         delete pkt->senderState;
+ 
+     delete pkt->req;
      delete pkt;
  }
  
@@@ -80,10 -85,6 +85,6 @@@ LSQUnit<Impl>::completeDataAccess(Packe
  
      if (isSwitchedOut() || inst->isSquashed()) {
          iewStage->decrWb(inst->seqNum);
-         delete state;
-         delete pkt->req;
-         delete pkt;
-         return;
      } else {
          if (!state->noWB) {
              writeback(inst, pkt);
@@@ -109,10 -110,13 +110,13 @@@ LSQUnit<Impl>::LSQUnit(
  
  template<class Impl>
  void
- LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
-                     unsigned maxSQEntries, unsigned id)
+ LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
+                     unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
  {
- //    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
+     cpu = cpu_ptr;
+     iewStage = iew_ptr;
+ 
+     DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
  
      switchedOut = false;
  
@@@ -140,19 -144,6 +144,6 @@@
      blockedLoadSeqNum = 0;
  }
  
- template<class Impl>
- void
- LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
- {
-     cpu = cpu_ptr;
- 
- #if USE_CHECKER
-     if (cpu->checker) {
-         cpu->checker->setDcachePort(dcachePort);
-     }
- #endif
- }
- 
  template<class Impl>
  std::string
  LSQUnit<Impl>::name() const
@@@ -209,6 -200,19 +200,19 @@@ LSQUnit<Impl>::regStats(
          .desc("Number of times an access to memory failed due to the cache being blocked");
  }
  
+ template<class Impl>
+ void
+ LSQUnit<Impl>::setDcachePort(Port *dcache_port)
+ {
+     dcachePort = dcache_port;
+ 
+ #if USE_CHECKER
+     if (cpu->checker) {
+         cpu->checker->setDcachePort(dcachePort);
+     }
+ #endif
+ }
+ 
  template<class Impl>
  void
  LSQUnit<Impl>::clearLQ()
@@@ -641,7 -645,20 +645,7 @@@ LSQUnit<Impl>::writebackStores(
          assert(!inst->memData);
          inst->memData = new uint8_t[64];
  
 -        TheISA::IntReg convertedData =
 -            TheISA::htog(storeQueue[storeWBIdx].data);
 -
 -        //FIXME This is a hack to get SPARC working. It, along with endianness
 -        //in the memory system in general, need to be straightened out more
 -        //formally. The problem is that the data's endianness is swapped when
 -        //it's in the 64 bit data field in the store queue. The data that you
 -        //want won't start at the beginning of the field anymore unless it was
 -        //a 64 bit access.
 -        memcpy(inst->memData,
 -                (uint8_t *)&convertedData +
 -                (TheISA::ByteOrderDiffers ?
 -                 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
 -                req->getSize());
 +        memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
  
          PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
                                          Packet::Broadcast);