# [DRAFT] Twin Multiply and Add Doubleword
+VA-Form
+
* madded RT,RA,RB,RC
Pseudo-code:
# [DRAFT] Twin Divide Quad Unsigned
-XO-Form
-
-* divmod2du RT,RA,RB (OE=0 Rc=0)
-* divmod2du. RT,RA,RB (OE=0 Rc=1)
-* divmod2duo RT,RA,RB (OE=1 Rc=0)
-* divmod2duo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-# Divide Word Extended Unsigned
-
-XO-Form
-
-* divweu RT,RA,RB (OE=0 Rc=0)
-* divweu. RT,RA,RB (OE=0 Rc=1)
-* divweuo RT,RA,RB (OE=1 Rc=0)
-* divweuo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-# Divide Word Extended Unsigned
-
-XO-Form
+VA-Form
-* divweu RT,RA,RB (OE=0 Rc=0)
-* divweu. RT,RA,RB (OE=0 Rc=1)
-* divweuo RT,RA,RB (OE=1 Rc=0)
-* divweuo. RT,RA,RB (OE=1 Rc=1)
+* divmod2du RT,RA,RB,RC
Pseudo-code:
- dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
- divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
- if divisor = [0]*(XLEN*2) then
- overflow <- 1
- else
+ <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below -->
+ <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
+ <!-- bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v] -->
+ if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
+ dividend[0:(XLEN*2)-1] <- (RA) || (RC)
+ divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
result <- dividend / divisor
modulo <- dividend % divisor
- if (RA) <u (RB) then
- RT <- result[XLEN:(XLEN*2)-1]
- RS <- modulo[XLEN:(XLEN*2)-1]
- overflow <- 0
- else
- overflow <- 1
- if overflow = 1 then
+ RT <- result[XLEN:(XLEN*2)-1]
+ RS <- modulo[XLEN:(XLEN*2)-1]
+ overflow <- 0
+ else
+ overflow <- 1
RT[0:XLEN-1] <- undefined([0]*XLEN)
RS[0:XLEN-1] <- undefined([0]*XLEN)