correct wishbone data directions

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 01dc9e567e40ea0b8c755b4046e96c80d4f3d1e2..75426e32cbb0561af37890f0998ded3e1af78d4e 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -35,9 +35,10 @@ entity toplevel is
        bram_we : out std_ulogic;
        bram_re : out std_ulogic;
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
-    bram_di   : inout std_logic_vector(63 downto 0);
-    bram_do   : out std_logic_vector(63 downto 0);
+    bram_di   : out std_logic_vector(63 downto 0);
+    bram_do   : in std_logic_vector(63 downto 0);
     bram_sel  : out std_logic_vector(7 downto 0);
+   
     
     -- for verilator debugging
     nia_req: out std_ulogic;

diff --git a/soc.vhdl b/soc.vhdl
index f46b3533613a58bf7f90a58958c2416e721a97ae..ca22e6f3d5d91f8790c7d94d45b4424facc787af 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -121,12 +121,12 @@ entity soc is
         ext_irq_eth          : in std_ulogic := '0';
         ext_irq_sdcard       : in std_ulogic := '0';
 
-    -- BRAM verilator access [FIXME]
+    -- BRAM verilator access [UNTESTED]
     bram_we : out std_ulogic;
     bram_re : out std_ulogic;
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
-    bram_di   : inout std_logic_vector(63 downto 0);
-    bram_do   : out std_logic_vector(63 downto 0);
+    bram_di   : out std_logic_vector(63 downto 0);
+    bram_do   : in std_logic_vector(63 downto 0);
     bram_sel  : out std_logic_vector(7 downto 0);
 
        -- UART0 signals: