namespace X86ISA
{
+ namespace ConditionTests
+ {
+ enum CondTest {
+ True,
+ NotFalse = True,
+ ECF,
+ EZF,
+ SZnZF,
+ MSTRZ,
+ STRZ,
+ MSTRC,
+ STRZnZF,
+ OF,
+ CF,
+ ZF,
+ CvZF,
+ SF,
+ PF,
+ SxOF,
+ SxOvZF,
+
+ False,
+ NotTrue = False,
+ NotECF,
+ NotEZF,
+ NotSZnZF,
+ NotMSTRZ,
+ NotSTRZ,
+ NotMSTRC,
+ NotSTRZnZF,
+ NotOF,
+ NotCF,
+ NotZF,
+ NotCvZF,
+ NotSF,
+ NotPF,
+ NotSxOF,
+ NotSxOvZF
+ };
+ }
+
/**
* Base classes for RegOps which provides a generateDisassembly method.
*/
- class RegOp : public X86MicroopBase
+ class RegOpBase : public X86MicroopBase
{
protected:
const RegIndex src1;
- const RegIndex src2;
const RegIndex dest;
- const bool setStatus;
const uint8_t dataSize;
- const uint8_t ext;
+ const uint16_t ext;
+
+ // Constructor
+ RegOpBase(ExtMachInst _machInst,
+ const char *mnem, const char *_instMnem,
+ bool isMicro, bool isDelayed,
+ bool isFirst, bool isLast,
+ RegIndex _src1, RegIndex _dest,
+ uint8_t _dataSize, uint16_t _ext,
+ OpClass __opClass) :
+ X86MicroopBase(_machInst, mnem, _instMnem,
+ isMicro, isDelayed, isFirst, isLast,
+ __opClass),
+ src1(_src1), dest(_dest),
+ dataSize(_dataSize), ext(_ext)
+ {
+ }
+
+ //Figure out what the condition code flags should be.
+ uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask,
+ uint64_t _dest, uint64_t _src1, uint64_t _src2) const;
+ bool checkCondition(uint64_t flags) const;
+ };
+
+ class RegOp : public RegOpBase
+ {
+ protected:
+ const RegIndex src2;
// Constructor
RegOp(ExtMachInst _machInst,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext,
+ uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
- X86MicroopBase(_machInst, mnem, _instMnem,
+ RegOpBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
+ _src1, _dest, _dataSize, _ext,
__opClass),
- src1(_src1), src2(_src2), dest(_dest),
- setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
+ src2(_src2)
{
}
const SymbolTable *symtab) const;
};
- class RegOpImm : public X86MicroopBase
+ class RegOpImm : public RegOpBase
{
protected:
- const RegIndex src1;
const uint8_t imm8;
- const RegIndex dest;
- const bool setStatus;
- const uint8_t dataSize;
- const uint8_t ext;
// Constructor
RegOpImm(ExtMachInst _machInst,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext,
+ uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
- X86MicroopBase(_machInst, mnem, _instMnem,
+ RegOpBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
+ _src1, _dest, _dataSize, _ext,
__opClass),
- src1(_src1), imm8(_imm8), dest(_dest),
- setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
+ imm8(_imm8)
{
}
%(op_decl)s;
%(op_rd)s;
- %(code)s;
- %(flag_code)s;
+
+ if(%(cond_check)s)
+ {
+ %(code)s;
+ %(flag_code)s;
+ }
//Write the resulting state to the execution context
if(fault == NoFault)
%(op_decl)s;
%(op_rd)s;
- %(code)s;
- %(flag_code)s;
+
+ if(%(cond_check)s)
+ {
+ %(code)s;
+ %(flag_code)s;
+ }
//Write the resulting state to the execution context
if(fault == NoFault)
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext);
+ uint8_t _dataSize, uint8_t _ext);
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext);
+ uint8_t _dataSize, uint8_t _ext);
%(BasicExecDeclare)s
};
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext);
+ uint8_t _dataSize, uint8_t _ext);
%(class_name)sImm(ExtMachInst _machInst,
const char * instMnem,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext);
+ uint8_t _dataSize, uint8_t _ext);
%(BasicExecDeclare)s
};
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
+ uint8_t _dataSize, uint8_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
- _src1, _src2, _dest, _setStatus, _dataSize, _ext,
+ _src1, _src2, _dest, _dataSize, _ext,
%(op_class)s)
{
buildMe();
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
+ uint8_t _dataSize, uint8_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
- _src1, _src2, _dest, _setStatus, _dataSize, _ext,
+ _src1, _src2, _dest, _dataSize, _ext,
%(op_class)s)
{
buildMe();
inline %(class_name)sImm::%(class_name)sImm(
ExtMachInst machInst, const char * instMnem,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
+ uint8_t _dataSize, uint8_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
- _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
+ _src1, _imm8, _dest, _dataSize, _ext,
%(op_class)s)
{
buildMe();
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
+ uint8_t _dataSize, uint8_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
- _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
+ _src1, _imm8, _dest, _dataSize, _ext,
%(op_class)s)
{
buildMe();
}};
let {{
+ class X86MicroMeta(type):
+ def __new__(mcls, name, bases, dict):
+ abstract = False
+ if "abstract" in dict:
+ abstract = dict['abstract']
+ del dict['abstract']
+
+ cls = type.__new__(mcls, name, bases, dict)
+ if not abstract:
+ allClasses[name] = cls
+ return cls
+
+ class XXX86Microop(object):
+ __metaclass__ = X86MicroMeta
+ abstract = True
+
class RegOp(X86Microop):
- def __init__(self, dest, src1, src2, setStatus):
+ abstract = True
+ def __init__(self, dest, src1, src2, flags):
self.dest = dest
self.src1 = src1
self.src2 = src2
- self.setStatus = setStatus
+ self.flags = flags
self.dataSize = "env.dataSize"
- self.ext = 0
+ if flags is None:
+ self.ext = 0
+ else:
+ if not isinstance(flags, (list, tuple)):
+ raise Exception, "flags must be a list or tuple of flags"
+ self.ext = " | ".join(flags)
+ self.className += "Flags"
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, mnemonic
%(flags)s, %(src1)s, %(src2)s, %(dest)s,
- %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
+ %(dataSize)s, %(ext)s)''' % {
"class_name" : self.className,
"flags" : self.microFlagsText(microFlags),
"src1" : self.src1, "src2" : self.src2,
"dest" : self.dest,
- "setStatus" : self.cppBool(self.setStatus),
"dataSize" : self.dataSize,
"ext" : self.ext}
return allocator
class RegOpImm(X86Microop):
- def __init__(self, dest, src1, imm8, setStatus):
+ abstract = True
+ def __init__(self, dest, src1, imm8, flags):
self.dest = dest
self.src1 = src1
self.imm8 = imm8
- self.setStatus = setStatus
+ self.flags = flags
self.dataSize = "env.dataSize"
- self.ext = 0
+ if flags is None:
+ self.ext = 0
+ else:
+ if not isinstance(flags, (list, tuple)):
+ raise Exception, "flags must be a list or tuple of flags"
+ self.ext = " | ".join(flags)
+ self.className += "Flags"
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, mnemonic
%(flags)s, %(src1)s, %(imm8)s, %(dest)s,
- %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
+ %(dataSize)s, %(ext)s)''' % {
"class_name" : self.className,
"flags" : self.microFlagsText(microFlags),
"src1" : self.src1, "imm8" : self.imm8,
"dest" : self.dest,
- "setStatus" : self.cppBool(self.setStatus),
"dataSize" : self.dataSize,
"ext" : self.ext}
return allocator
decoder_output = ""
exec_output = ""
- def setUpMicroRegOp(name, Name, base, code, child, flagCode):
+ # A function which builds the C++ classes that implement the microops
+ def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck):
global header_output
global decoder_output
global exec_output
iop = InstObjParams(name, Name, base,
{"code" : code,
- "flag_code" : flagCode})
+ "flag_code" : flagCode,
+ "cond_check" : condCheck})
header_output += MicroRegOpDeclare.subst(iop)
decoder_output += MicroRegOpConstructor.subst(iop)
exec_output += MicroRegOpExecute.subst(iop)
- microopClasses[name] = child
- def defineMicroRegOp(mnemonic, code, flagCode):
+ checkCCFlagBits = "checkCondition(ccFlagBits)"
+ genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);"
+
+
+ # This creates a python representations of a microop which are a cross
+ # product of reg/immediate and flag/no flag versions.
+ def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False):
Name = mnemonic
name = mnemonic.lower()
regCode = matcher.sub("SrcReg2", code)
immCode = matcher.sub("imm8", code)
- # Build the all register version of this micro op
+ if not cc:
+ flagCode = genCCFlagBits % secondSrc
+ condCode = "true"
+ else:
+ flagCode = ""
+ condCode = checkCCFlagBits
+
+ regFlagCode = matcher.sub("SrcReg2", flagCode)
+ immFlagCode = matcher.sub("imm8", flagCode)
+
class RegOpChild(RegOp):
- def __init__(self, dest, src1, src2, setStatus=False):
- super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
- self.className = Name
- self.mnemonic = name
+ mnemonic = name
+ className = Name
+ def __init__(self, dest, src1, src2, flags=None):
+ super(RegOpChild, self).__init__(dest, src1, src2, flags)
+
+ microopClasses[name] = RegOpChild
- setUpMicroRegOp(name, Name, "X86ISA::RegOp", \
- regCode, RegOpChild, flagCode);
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
+ setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode);
- # Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
- def __init__(self, dest, src1, src2, setStatus=False):
- super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
- self.className = Name + "Imm"
- self.mnemonic = name + "i"
-
- setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
- immCode, RegOpChildImm, flagCode);
-
- defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
- defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
- defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
- defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
- defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
- defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
- defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
- defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
- defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
+ mnemonic = name + 'i'
+ className = Name + 'Imm'
+ def __init__(self, dest, src1, src2, flags=None):
+ super(RegOpChildImm, self).__init__(dest, src1, src2, flags)
+
+ microopClasses[name + 'i'] = RegOpChildImm
+
+ setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
+ setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode);
+
+ defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
+ defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
+ defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
+ defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
+ defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
+ defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
+ defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
+ defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2')
+ defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True)
# This has it's own function because Wr ops have implicit destinations
def defineMicroRegOpWr(mnemonic, code):
regCode = matcher.sub("SrcReg2", code)
immCode = matcher.sub("imm8", code)
- # Build the all register version of this micro op
class RegOpChild(RegOp):
- def __init__(self, src1, src2):
- super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
- self.className = Name
- self.mnemonic = name
+ mnemonic = name
+ className = Name
+ def __init__(self, src1, src2, flags=None):
+ super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags)
+
+ microopClasses[name] = RegOpChild
- setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
+ setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits);
- # Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
+ mnemonic = name
+ className = Name
def __init__(self, src1, src2):
- super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
- self.className = Name + "Imm"
- self.mnemonic = name + "i"
+ super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None)
+
+ microopClasses[name + 'i'] = RegOpChildImm
- setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
- immCode, RegOpChildImm, "");
+ setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
+ setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits);
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
class RegOpChild(RegOp):
def __init__(self, dest, src1 = "NUM_INTREGS"):
- super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
+ super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None)
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
+ microopClasses[name] = RegOpChild
+
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true");
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
class RegOpChild(RegOpImm):
def __init__(self, dest, src1, src2):
- super(RegOpChild, self).__init__(dest, src1, src2, False)
+ super(RegOpChild, self).__init__(dest, src1, src2, None)
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
+ microopClasses[name] = RegOpChild
+
+ setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true");
defineMicroRegOpImm('Sext', '''
IntReg val = SrcReg1;