see soc/fu/trap/main_stage.py trap() function, and:

https://libre-soc.org/irclog/%23libre-soc.2022-01-18.log.html#t2022-01-18T13:21:25
bits of SRR1 need to be preserved on an interrupt, which means that
PowerDecoder2 must schedule a read of SRR1.  the Power ISA spec
is extremely obscure and obtuse on which bits must be preserved,
therefore it is just easier to copy microwatt behaviour

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index a8ff85329a73f3d217dac2f0c22e9bdf1d0479b9..cb054735fbcb33dd2403c0bb6c1dbb288e95d30f 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1570,6 +1570,12 @@ class PowerDecode2(PowerDecodeSubset):
         # Note: OP_SC could actually be modified to just be a trap
         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
                   (do_out.insn_type == MicrOp.OP_SC)):
+            # see fu/trap/main_stage.py trap() function: some bits of SRR1
+            # need to be preserved, rather than just blithely overwrite MSR.
+            # following microwatt, here.
+            # TRAP read fast2 = SRR1
+            comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
+            comb += e_out.read_fast2.ok.eq(1)
             # TRAP write fast1 = SRR0
             comb += e_out.write_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
             comb += e_out.write_fast1.ok.eq(1)