comments

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 3a0452fc1d2b9bf6f6534cbe827e646715b132c5..2f21295815cfabf68f10a0729d4792e8956dedf7 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -66,6 +66,9 @@ special_sprs = {
     'VRSAVE': 256}
 
 
+# rrright.  this is here basically because the compiler pywriter returns
+# results in a specific priority order.  to make sure regs match up they
+# need partial sorting. sigh.
 REG_SORT_ORDER = {
     # TODO (lkcl): adjust other registers that should be in a particular order
     # probably CA, CA32, and CR