Fix handling of z_digit "?" and fix optimization of cmp with "z"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 5da88a93f1af3447f1d217adc660968402dc8d31..49281f7e79e6874bf16f3b523b28adb90c0c240c 100644 (file)
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -85,10 +85,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
                        digits.push_back(10 + *str - 'A');
                else if (*str == 'x' || *str == 'X')
                        digits.push_back(0xf0);
-               else if (*str == 'z' || *str == 'Z')
+               else if (*str == 'z' || *str == 'Z' || *str == '?')
                        digits.push_back(0xf1);
-               else if (*str == '?')
-                       digits.push_back(0xf2);
                str++;
        }
 
@@ -112,8 +110,6 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
                                        data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx);
                                else if (*it == 0xf1)
                                        data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz);
-                               else if (*it == 0xf2)
-                                       data.push_back(RTLIL::Sa);
                                else
                                        data.push_back((*it & bitmask) ? State::S1 : State::S0);
                        }

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 00d7d6063cc275c85be6c2c9848ae211a36aea8a..6cf66fb95aec858f38e17ca1522c169c65d885ad 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        }
 
                        if (b.is_fully_const()) {
+                               if (b.is_fully_undef()) {
+                                       RTLIL::SigSpec input = b;
+                                       ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y))));
+                               } else
                                if (b.as_bool() == (cell->type == ID($eq))) {
                                        RTLIL::SigSpec input = b;
                                        ACTION_DO(ID::Y, cell->getPort(ID::A));