whitespace

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index be7db76a9c4b8c39edc863f6fe8c2b6cdc81321f..80d6296c57bae6b936bd2b8c3357bd32aa214e79 100644 (file)
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -1,9 +1,12 @@
 # SV setvl
 
-sv.setvl allows optional setting of both MVL and of indirectly marking one of the scalar registers as being VL.
+sv.setvl allows optional setting of both MVL and of indirectly marking
+one of the scalar registers as being VL.
 
-Unlike the majority of other CSRs, which contain status bits that change behaviour, VL is closely interlinked with the instructions it affects and often requires arithmetic interaction.
-Thus it makes more sense to actually *use* one of the scalar registers *as* VL.
+Unlike the majority of other CSRs, which contain status bits that change
+behaviour, VL is closely interlinked with the instructions it affects
+and often requires arithmetic interaction.  Thus it makes more sense to
+actually *use* one of the scalar registers *as* VL.
 
 Format for Vector Configuration Instructions under OP-V major opcode: