Set Architecture (ISA) of the past sixty years. With NLnet's help we have
TRL (3) implementations and simulations demonstrating a 75% reduction in
the program size of core algorithms for Video and Audio DSP Processing
-(FFT, DCT, Matrix Multiply), and these still need optimized, which if
+(FFT, DCT, Matrix Multiply), and these still have room for optimisation,
+which if
successfully expanded to general-purpose algorithms would result in huge
power savings if deployed in mass-volume end-user products.