Use CSRPrefixProxy for exposing CSR

diff --git a/gram/core/__init__.py b/gram/core/__init__.py
index a570ad390ca48ae9365930fe618ff77048aa0c8d..8ca06c9b598e75729334d68b7b223a2f73c3ab7f 100644 (file)
--- a/gram/core/__init__.py
+++ b/gram/core/__init__.py
@@ -3,6 +3,7 @@ from nmigen import *
 from lambdasoc.periph import Peripheral
 
 from gram.dfii import DFIInjector
+from gram.compat import CSRPrefixProxy
 from gram.core.controller import ControllerSettings, gramController
 from gram.core.crossbar import gramCrossbar
 
@@ -10,31 +11,48 @@ from gram.core.crossbar import gramCrossbar
 
 class gramCore(Peripheral, Elaboratable):
     def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs):
+        super().__init__()
+
+        bank = self.csr_bank()
+        
+        self._zero_ev = self.event(mode="rise")
+
         self._phy = phy
         self._geom_settings = geom_settings
         self._timing_settings = timing_settings
         self._clk_freq = clk_freq
         self._kwargs = kwargs
 
-    def elaborate(self, platform):
-        m = Module()
-
-        m.submodules.dfii = dfii = DFIInjector(
+        self.dfii = DFIInjector(
+            csr_bank = CSRPrefixProxy(bank, "dfii"),
             addressbits = self._geom_settings.addressbits,
             bankbits    = self._geom_settings.bankbits,
             nranks      = self._phy.settings.nranks,
             databits    = self._phy.settings.dfi_databits,
             nphases     = self._phy.settings.nphases)
-        m.d.comb += dfii.master.connect(self._phy.dfi)
 
-        m.submodules.controller = controller = gramController(
+        self.controller = gramController(
             phy_settings    = self._phy.settings,
             geom_settings   = self._geom_settings,
             timing_settings = self._timing_settings,
             clk_freq        = self._clk_freq,
             **self._kwargs)
-        m.d.comb += controller.dfi.connect(dfii.slave)
 
-        m.submodules.crossbar = gramCrossbar(controller.interface)
+        self.crossbar = gramCrossbar(self.controller.interface)
+
+        self._bridge  = self.bridge(data_width=32, granularity=8, alignment=2)
+        self.bus = self._bridge.bus
+        self.irq = self._bridge.irq
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.submodules += self.dfii
+        m.d.comb += self.dfii.master.connect(self._phy.dfi)
+
+        m.submodules.controller = self.controller
+        m.d.comb += self.controller.dfi.connect(self.dfii.slave)
+
+        m.submodules += self.crossbar
 
         return m

diff --git a/gram/dfii.py b/gram/dfii.py
index 45abdb2f73ec2d25fd2c510fd7d787fbfcab5a8e..0c7741f2f93bc48cf7c8110b032881451036c4dd 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -6,21 +6,19 @@
 from nmigen import *
 
 from gram.phy import dfi
+from gram.compat import CSRPrefixProxy
 from lambdasoc.periph import Peripheral
 
 # PhaseInjector ------------------------------------------------------------------------------------
 
-class PhaseInjector(Peripheral, Elaboratable):
-    def __init__(self, phase):
-        super().__init__(name = "phaseinjector")
-
-        bank = self.csr_bank()
-        self._command = bank.csr(6, "rw")
-        self._command_issue = bank.csr(1, "rw")
-        self._address = bank.csr(len(phase.address), "rw")
-        self._baddress = bank.csr(len(phase.bank), "rw")
-        self._wrdata = bank.csr(len(phase.wrdata), "rw")
-        self._rddata = bank.csr(len(phase.rddata), "rw")
+class PhaseInjector(Elaboratable):
+    def __init__(self, csr_bank, phase):
+        self._command = csr_bank.csr(6, "rw")
+        self._command_issue = csr_bank.csr(1, "rw")
+        self._address = csr_bank.csr(len(phase.address), "rw")
+        self._baddress = csr_bank.csr(len(phase.bank), "rw")
+        self._wrdata = csr_bank.csr(len(phase.wrdata), "rw")
+        self._rddata = csr_bank.csr(len(phase.rddata), "rw")
 
         self._phase = phase
 
@@ -58,24 +56,24 @@ class PhaseInjector(Peripheral, Elaboratable):
 
 # DFIInjector --------------------------------------------------------------------------------------
 
-class DFIInjector(Peripheral, Elaboratable):
-    def __init__(self, addressbits, bankbits, nranks, databits, nphases=1):
-        super().__init__(name = "dfii")
-
+class DFIInjector(Elaboratable):
+    def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
         self._nranks = nranks
 
         self._inti  = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
         self.slave  = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
         self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
 
-        bank = self.csr_bank()
-        self._control = bank.csr(4, "rw")  # sel, cke, odt, reset_n
+        self._control = csr_bank.csr(4, "rw")  # sel, cke, odt, reset_n
+
+        self._phases = []
+        for n, phase in enumerate(self._inti.phases):
+            self._phases += [PhaseInjector(CSRPrefixProxy(csr_bank, "p{}".format(n)), phase)]
 
     def elaborate(self, platform):
         m = Module()
 
-        for n, phase in enumerate(self._inti.phases):
-            m.submodules += PhaseInjector(phase)
+        m.submodules += self._phases
 
         with m.If(self._control.r_data[0]):
             m.d.comb += self.slave.connect(self.master)