va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
+ cb->cb_color_base = va >> 8;
+
if (device->physical_device->rad_info.chip_class >= GFX9) {
struct gfx9_surf_meta_flags meta;
if (iview->image->dcc_offset)
S_028C74_RB_ALIGNED(meta.rb_aligned) |
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
- va += iview->image->surface.u.gfx9.surf_offset >> 8;
+ cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
} else {
const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
- va += level_info->offset;
+ cb->cb_color_base += level_info->offset >> 8;
+ if (level_info->mode == RADEON_SURF_MODE_2D)
+ cb->cb_color_base |= iview->image->surface.tile_swizzle;
pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
}
}
- cb->cb_color_base = va >> 8;
- if (device->physical_device->rad_info.chip_class < GFX9)
- cb->cb_color_base |= iview->image->surface.tile_swizzle;
/* CMASK variables */
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->cmask.offset;