Simple bus base class

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index cd06436cdbdf0631b006c7a5f825e5e4577cf013..f4fdcad0a002bb7087c870fcb770b86a761fd8e4 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -1,21 +1,20 @@
 from migen.fhdl import structure as f
-from functools import partial
+from .simple import Simple
 
-class Master:
+_desc = [
+       (True,  "a",    16),
+       (True,  "we",   1),
+       (True,  "d",    32),
+       (False, "d",    32)
+]
+
+class Master(Simple):
        def __init__(self):
-               d = partial(f.Declare, self)
-               d("a_o", f.BV(16))
-               d("we_o")
-               d("d_o", f.BV(32))
-               d("d_i", f.BV(32))
+               Simple.__init__(self, _desc, False)
 
-class Slave:
+class Slave(Simple):
        def __init__(self):
-               d = partial(f.Declare, self)
-               d("a_i", f.BV(16))
-               d("we_i")
-               d("d_i", f.BV(32))
-               d("d_o", f.BV(32))
+               Simple.__init__(self, _desc, True)
 
 class Interconnect:
        def __init__(self, master, slaves):
@@ -32,4 +31,4 @@ class Interconnect:
                        comb.append(a(slave.d_i, self.master.d_o))
                        rb = rb | slave.d_o
                comb.append(a(master.d_i, rb))
-               return f.Fragment(comb)
\ No newline at end of file
+               return f.Fragment(comb)

diff --git a/migen/bus/simple.py b/migen/bus/simple.py
new file mode 100644 (file)
index 0000000..8ca2799
--- /dev/null
+++ b/migen/bus/simple.py
@@ -0,0 +1,17 @@
+from migen.fhdl import structure as f
+
+# desc is a list of tuples, each made up of:
+# 0) boolean: "master to slave"
+# 1) string: name
+# 2) int: width
+class Simple():
+       def __init__(self, desc, slave):
+               for signal in desc:
+                       if signal[0] ^ slave:
+                               suffix = "_o"
+                       else:
+                               suffix = "_i"
+                       modules = self.__module__.split('.')
+                       busname = modules[len(modules)-1]
+                       signame = signal[1]+suffix
+                       setattr(self, signame, f.Signal(f.BV(signal[2]), busname+"_"+signame))

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index f3ff20443ad4751dbb94be900988b69705ea00ed..254667aa7735aed2d05d6b90afb241b43fa84ec8 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -117,7 +117,7 @@ class Signal(Value):
                return id(self)
 
 def Declare(parent, name, bv=BV(), variable=False, reset=0):
-       setattr(parent, name, Signal(bv, parent.__class__.__name__+"_"+name, variable, reset))
+       setattr(parent, name, Signal(bv, parent.__class__.__name__ + "_" + name, variable, reset))
 
 # statements