(no commit message)

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index d8e60039f8e1964c9ffb65b75bb26c204745feb9..ad124adeb700014683e2808e7b5dce0c1fea485d 100644 (file)
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -146,6 +146,12 @@ raised.
   replacement for dsl.Module, called dsl.SIMDModule (or other).
 * **Monkey-patching dsl.Module**. This idea intrusively modifies dsl.Module
   with external functions.
+* **Compilers / Macros**. On the basis that if this was VHDL or Verilog
+  one technique for creating SIMD variants of the required code would be
+  to use macro substitution or crude compilers to autogenerate the dynamic
+  SIMD from VHDL / Verilog templates, why not do exactly the same thing.
+  Design a SIMD langusge, write python in that, and have it output
+  nmigen HDL.
 
 All of these ideas, unfortunately, are extremely costly in many different ways: