Added support for parsing attributes on port connections.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8244a8f444d231e174a64eeda3094699c7a9595a..82a1d9d39ef333fd5530f0733e8672812e4558a5 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1532,27 +1532,27 @@ cell_port_list_rules:
        cell_port | cell_port_list_rules ',' cell_port;
 
 cell_port:
-       /* empty */ {
+       attr {
                AstNode *node = new AstNode(AST_ARGUMENT);
                astbuf2->children.push_back(node);
        } |
-       expr {
+       attr expr {
                AstNode *node = new AstNode(AST_ARGUMENT);
                astbuf2->children.push_back(node);
-               node->children.push_back($1);
+               node->children.push_back($2);
        } |
-       '.' TOK_ID '(' expr ')' {
+       attr '.' TOK_ID '(' expr ')' {
                AstNode *node = new AstNode(AST_ARGUMENT);
-               node->str = *$2;
+               node->str = *$3;
                astbuf2->children.push_back(node);
-               node->children.push_back($4);
-               delete $2;
+               node->children.push_back($5);
+               delete $3;
        } |
-       '.' TOK_ID '(' ')' {
+       attr '.' TOK_ID '(' ')' {
                AstNode *node = new AstNode(AST_ARGUMENT);
-               node->str = *$2;
+               node->str = *$3;
                astbuf2->children.push_back(node);
-               delete $2;
+               delete $3;
        };
 
 always_stmt: