frv.md (movdi, movdf): Handle wide-constant splits with wider-than-32-bit HOST_WIDE_INTs.

* config/frv/frv.md (movdi, movdf): Handle wide-constant splits
with wider-than-32-bit HOST_WIDE_INTs.

From-SVN: r89524

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ce83ce91299045e9d01f20a96c9fd53f5eacdc74..e216c9ac83c9d521bdff777d2227d7a4320b4d6f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-10-25  Alexandre Oliva  <aoliva@redhat.com>
+
+       * config/frv/frv.md (movdi, movdf): Handle wide-constant splits
+       with wider-than-32-bit HOST_WIDE_INTs.
+
 2004-10-25  David Billinghurst <David.Billinghurst@riotinto.com>
 
        * config/mips/mips.c(mips_output_filename): Remove unused 

diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index ee17edabed8561a095e4ee00ea5759c6005c10f8..21eef863b6570e24f464fc549990aeb0b7a4acb8 100644 (file)
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -1833,7 +1833,7 @@
        (match_operand:DI 1 "const_int_operand" ""))]
   "reload_completed"
   [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 1))]
+   (set (match_dup 3) (match_dup 5))]
   "
 {
   rtx op0 = operands[0];
@@ -1841,7 +1841,18 @@
 
   operands[2] = gen_highpart (SImode, op0);
   operands[3] = gen_lowpart (SImode, op0);
-  operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
+  if (HOST_BITS_PER_WIDE_INT <= 32)
+    {
+      operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
+      operands[5] = op1;
+    }
+  else
+    {
+      operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
+                             >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31)
+                            - ((unsigned HOST_WIDE_INT)1 << 31));
+      operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
+    }
 }")
 
 (define_split
@@ -2031,7 +2042,7 @@
        (match_operand:DF 1 "const_int_operand" ""))]
   "reload_completed"
   [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 1))]
+   (set (match_dup 3) (match_dup 5))]
   "
 {
   rtx op0 = operands[0];
@@ -2039,7 +2050,18 @@
 
   operands[2] = gen_highpart (SImode, op0);
   operands[3] = gen_lowpart (SImode, op0);
-  operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
+  if (HOST_BITS_PER_WIDE_INT <= 32)
+    {
+      operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
+      operands[5] = op1;
+    }
+  else
+    {
+      operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
+                             >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31)
+                            - ((unsigned HOST_WIDE_INT)1 << 31));
+      operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
+    }
 }")
 
 (define_split