genxml: Rename two MCS fields to Auxiliary Surface on gen7

This makes gen7 more consistent with gen8+

Reviewed-by: Chad Versace <chadversary@chromium.org>

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 3f3b188221837e1a9534bbe178c396f8f4b6d8c1..40927efcea999437d6ac597e6d236b8aa8db994d 100644 (file)
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -672,8 +672,8 @@
     <field name="MIP Count / LOD" start="160" end="163" type="uint"/>
     <field name="Append Counter Address" start="198" end="223" type="address"/>
     <field name="Append Counter Enable" start="193" end="193" type="bool"/>
-    <field name="MCS Base Address" start="204" end="223" type="address"/>
-    <field name="MCS Surface Pitch" start="195" end="203" type="uint"/>
+    <field name="Auxiliary Surface Base Address" start="204" end="223" type="address"/>
+    <field name="Auxiliary Surface Pitch" start="195" end="203" type="uint"/>
     <field name="MCS Enable" start="192" end="192" type="bool"/>
     <field name="Reserved: MBZ" start="222" end="223" type="uint"/>
     <field name="X Offset for UV Plane" start="208" end="221" type="uint"/>

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 91fe02f048f853f56e1a69d0512adc1a9b8402a4..7b5c2af2de1bf2e40a1f05a330a85c56e184ea93 100644 (file)
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -683,8 +683,8 @@
     <field name="MIP Count / LOD" start="160" end="163" type="uint"/>
     <field name="Append Counter Address" start="198" end="223" type="address"/>
     <field name="Append Counter Enable" start="193" end="193" type="bool"/>
-    <field name="MCS Base Address" start="204" end="223" type="address"/>
-    <field name="MCS Surface Pitch" start="195" end="203" type="uint"/>
+    <field name="Auxiliary Surface Base Address" start="204" end="223" type="address"/>
+    <field name="Auxiliary Surface Pitch" start="195" end="203" type="uint"/>
     <field name="MCS Enable" start="192" end="192" type="bool"/>
     <field name="Reserved: MBZ" start="222" end="223" type="uint"/>
     <field name="X Offset for UV Plane" start="208" end="221" type="uint"/>

diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 853bb11846244c88294528753866095faac1f0be..fa464694862895ff8ba8d8a23f48cb0e3151f4d3 100644 (file)
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -548,16 +548,17 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       uint32_t pitch_in_tiles =
          info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
 
+      s.AuxiliarySurfaceBaseAddress = info->aux_address;
+      s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
+
 #if GEN_GEN >= 8
       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
-      s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
       /* Auxiliary surfaces in ISL have compressed formats but the hardware
        * doesn't expect our definition of the compression, it expects qpitch
        * in units of samples on the main surface.
        */
       s.AuxiliarySurfaceQPitch =
          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
-      s.AuxiliarySurfaceBaseAddress = info->aux_address;
 
       if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
          /* The number of samples must be 1 */
@@ -582,8 +583,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 #else
       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
              info->aux_usage == ISL_AUX_USAGE_CCS_D);
-      s.MCSBaseAddress = info->aux_address,
-      s.MCSSurfacePitch = pitch_in_tiles - 1;
       s.MCSEnable = true;
 #endif
    }