Use analysis mode if set in file

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b130edbdc1dab8b971c1b140ef84eaedf139de2a..29131fdc591103e0fbc5d8e3ef304a586994dd4e 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2717,7 +2717,7 @@ struct VerificPass : public Pass {
 
                if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
                {
-                       unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific
+                       unsigned verilog_mode = veri_file::UNDEFINED;
                        bool is_formal = false;
                        const char* filename = nullptr;
 
@@ -2764,7 +2764,7 @@ struct VerificPass : public Pass {
                        veri_file::DefineMacro("VERIFIC");
                        veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
 
-                       if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
+                       if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {
                                verific_error_msg.clear();
                                log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
                        }