These types are being replaced with uint64_t and int64_t.
RubyDirectedTester(const RubyDirectedTester& obj);
RubyDirectedTester& operator=(const RubyDirectedTester& obj);
- uint64 m_requests_completed;
+ uint64_t m_requests_completed;
std::vector<MasterPort*> ports;
- uint64 m_requests_to_complete;
+ uint64_t m_requests_to_complete;
DirectedGenerator* generator;
};
std::vector<Cycles> m_last_progress_vector;
int m_num_cpus;
- uint64 m_checks_completed;
+ uint64_t m_checks_completed;
std::vector<MasterPort*> writePorts;
std::vector<MasterPort*> readPorts;
- uint64 m_checks_to_complete;
+ uint64_t m_checks_to_complete;
int m_deadlock_threshold;
int m_num_writers;
int m_num_readers;
}
void
-Histogram::add(int64 value)
+Histogram::add(int64_t value)
{
assert(value >= 0);
m_max = max(m_max, value);
Histogram(int binsize = 1, uint32_t bins = 50);
~Histogram();
- void add(int64 value);
+ void add(int64_t value);
void add(Histogram& hist);
void doubleBinSize();
uint64_t size() const { return m_count; }
uint32_t getBins() const { return m_data.size(); }
int getBinSize() const { return m_binsize; }
- int64 getTotal() const { return m_sumSamples; }
+ int64_t getTotal() const { return m_sumSamples; }
uint64_t getSquaredTotal() const { return m_sumSquaredSamples; }
uint64_t getData(int index) const { return m_data[index]; }
- int64 getMax() const { return m_max; }
+ int64_t getMax() const { return m_max; }
void printWithMultiplier(std::ostream& out, double multiplier) const;
void printPercent(std::ostream& out) const;
private:
std::vector<uint64_t> m_data;
- int64 m_max; // the maximum value seen so far
+ int64_t m_max; // the maximum value seen so far
uint64_t m_count; // the number of elements added
int m_binsize; // the size of each bucket
uint32_t m_largest_bin; // the largest bin used
- int64 m_sumSamples; // the sum of all samples
+ int64_t m_sumSamples; // the sum of all samples
uint64_t m_sumSquaredSamples; // the sum of the square of all samples
double getStandardDeviation() const;
#ifndef TYPEDEFINES_H
#define TYPEDEFINES_H
-typedef unsigned long long uint64;
-typedef long long int64;
-
typedef unsigned int LinkID;
typedef unsigned int NodeID;
typedef unsigned int SwitchID;
int
H3BloomFilter::get_index(Addr addr, int i)
{
- uint64 x = makeLineAddress(addr);
- // uint64 y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
+ uint64_t x = makeLineAddress(addr);
+ // uint64_t y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
int y = hash_H3(x,i);
if (isParallel) {
}
int
-H3BloomFilter::hash_H3(uint64 value, int index)
+H3BloomFilter::hash_H3(uint64_t value, int index)
{
- uint64 mask = 1;
- uint64 val = value;
+ uint64_t mask = 1;
+ uint64_t val = value;
int result = 0;
for (int i = 0; i < 64; i++) {
private:
int get_index(Addr addr, int hashNumber);
- int hash_H3(uint64 value, int index);
+ int hash_H3(uint64_t value, int index);
std::vector<int> m_filter;
int m_filter_size;
// m_skip_bits is used to perform BitSelect after skipping some
// bits. Used to simulate BitSel hashing on larger than cache-line
// granularities
- uint64 x = (makeLineAddress(addr) >> m_skip_bits);
+ uint64_t x = (makeLineAddress(addr) >> m_skip_bits);
int y = hash_bitsel(x, i, m_num_hashes, 30, m_filter_size_bits);
//36-bit addresses, 6-bit cache lines
}
int
-MultiBitSelBloomFilter::hash_bitsel(uint64 value, int index, int jump,
+MultiBitSelBloomFilter::hash_bitsel(uint64_t value, int index, int jump,
int maxBits, int numBits)
{
- uint64 mask = 1;
+ uint64_t mask = 1;
int result = 0;
int bit, i;
private:
int get_index(Addr addr, int hashNumber);
- int hash_bitsel(uint64 value, int index, int jump, int maxBits,
+ int hash_bitsel(uint64_t value, int index, int jump, int maxBits,
int numBits);
std::vector<int> m_filter;
int m_not_avail_count; // count the # of times I didn't have N
// slots available
- uint64 m_msg_counter;
+ uint64_t m_msg_counter;
int m_priority_rank;
const bool m_strict_fifo;
const bool m_randomization;
private:
Addr m_addr;
- uint64 m_loads;
- uint64 m_stores;
- uint64 m_atomics;
- uint64 m_total;
- uint64 m_user;
- uint64 m_sharing;
+ uint64_t m_loads;
+ uint64_t m_stores;
+ uint64_t m_atomics;
+ uint64_t m_total;
+ uint64_t m_user;
+ uint64_t m_sharing;
Set m_touched_by;
Histogram* m_histogram_ptr;
};
{
const int records_printed = 100;
- uint64 misses = 0;
+ uint64_t misses = 0;
std::vector<const AccessTraceForAddress *> sorted;
AddressMap::const_iterator i = record_map.begin();
Histogram all_records_log(-1);
// Allows us to track how many lines where touched by n processors
- std::vector<int64> m_touched_vec;
- std::vector<int64> m_touched_weighted_vec;
+ std::vector<int64_t> m_touched_vec;
+ std::vector<int64_t> m_touched_weighted_vec;
m_touched_vec.resize(num_of_sequencers+1);
m_touched_weighted_vec.resize(num_of_sequencers+1);
for (int j = 0; j < m_touched_vec.size(); j++) {
AddressProfiler(const AddressProfiler& obj);
AddressProfiler& operator=(const AddressProfiler& obj);
- int64 m_sharing_miss_counter;
+ int64_t m_sharing_miss_counter;
AddressMap m_dataAccessTrace;
AddressMap m_macroBlockAccessTrace;
bool StoreTrace::s_init = false; // Total number of store lifetimes of
// all lines
-int64 StoreTrace::s_total_samples = 0; // Total number of store
+int64_t StoreTrace::s_total_samples = 0; // Total number of store
// lifetimes of all lines
Histogram* StoreTrace::s_store_count_ptr = NULL;
Histogram* StoreTrace::s_store_first_to_stolen_ptr = NULL;
private:
static bool s_init;
- static int64 s_total_samples; // Total number of store lifetimes
+ static int64_t s_total_samples; // Total number of store lifetimes
// of all lines
static Histogram* s_store_count_ptr;
static Histogram* s_store_first_to_stolen_ptr;
Tick m_last_store;
int m_stores_this_interval;
- int64 m_total_samples; // Total number of store lifetimes of this line
+ int64_t m_total_samples; // Total number of store lifetimes of this line
Histogram m_store_count;
Histogram m_store_first_to_stolen;
Histogram m_store_last_to_stolen;
}
bool
-BankedArray::tryAccess(int64 idx)
+BankedArray::tryAccess(int64_t idx)
{
if (accessLatency == 0)
return true;
}
void
-BankedArray::reserve(int64 idx)
+BankedArray::reserve(int64_t idx)
{
if (accessLatency == 0)
return;
}
unsigned int
-BankedArray::mapIndexToBank(int64 idx)
+BankedArray::mapIndexToBank(int64_t idx)
{
if (banks == 1) {
return 0;
{
public:
AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
- int64 idx;
+ int64_t idx;
Tick startAccess;
Tick endAccess;
};
// otherwise, schedule the event and wait for it to complete
std::vector<AccessRecord> busyBanks;
- unsigned int mapIndexToBank(int64 idx);
+ unsigned int mapIndexToBank(int64_t idx);
public:
BankedArray(unsigned int banks, Cycles accessLatency,
// Note: We try the access based on the cache index, not the address
// This is so we don't get aliasing on blocks being replaced
- bool tryAccess(int64 idx);
+ bool tryAccess(int64_t idx);
- void reserve(int64 idx);
+ void reserve(int64_t idx);
Cycles getLatency() const { return accessLatency; }
};
}
// convert a Address to its location in the cache
-int64
+int64_t
CacheMemory::addressToCacheSet(Addr address) const
{
assert(address == makeLineAddress(address));
// Given a cache index: returns the index of the tag in a set.
// returns -1 if the tag is not found.
int
-CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const
+CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const
{
assert(tag == makeLineAddress(tag));
// search the set for the tags
// Given a cache index: returns the index of the tag in a set.
// returns -1 if the tag is not found.
int
-CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
+CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet,
Addr tag) const
{
assert(tag == makeLineAddress(tag));
{
assert(address == makeLineAddress(address));
DPRINTF(RubyCache, "address: %s\n", address);
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc != -1) {
// Do we even have a tag match?
{
assert(address == makeLineAddress(address));
DPRINTF(RubyCache, "address: %s\n", address);
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc != -1) {
CacheMemory::isTagPresent(Addr address) const
{
assert(address == makeLineAddress(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc == -1) {
{
assert(address == makeLineAddress(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
for (int i = 0; i < m_cache_assoc; i++) {
AbstractCacheEntry* entry = m_cache[cacheSet][i];
DPRINTF(RubyCache, "address: %s\n", address);
// Find the first open slot
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
for (int i = 0; i < m_cache_assoc; i++) {
if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
assert(address == makeLineAddress(address));
assert(isTagPresent(address));
DPRINTF(RubyCache, "address: %s\n", address);
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc != -1) {
delete m_cache[cacheSet][loc];
assert(address == makeLineAddress(address));
assert(!cacheAvail(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
m_Address;
}
CacheMemory::lookup(Addr address)
{
assert(address == makeLineAddress(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if(loc == -1) return NULL;
return m_cache[cacheSet][loc];
CacheMemory::lookup(Addr address) const
{
assert(address == makeLineAddress(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if(loc == -1) return NULL;
return m_cache[cacheSet][loc];
void
CacheMemory::setMRU(Addr address)
{
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if(loc != -1)
void
CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
{
- uint64 warmedUpBlocks = 0;
- uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets
- * (uint64)m_cache_assoc;
+ uint64_t warmedUpBlocks = 0;
+ uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets *
+ (uint64_t)m_cache_assoc;
for (int i = 0; i < m_cache_num_sets; i++) {
for (int j = 0; j < m_cache_assoc; j++) {
DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks"
"recorded %.2f%% \n", name().c_str(), warmedUpBlocks,
- (uint64)m_cache_num_sets * (uint64)m_cache_assoc,
- (float(warmedUpBlocks)/float(totalBlocks))*100.0);
+ totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0);
}
void
{
DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
assert(address == makeLineAddress(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
m_cache[cacheSet][loc]->setLocked(context);
{
DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
assert(address == makeLineAddress(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
m_cache[cacheSet][loc]->clearLocked();
CacheMemory::isLocked(Addr address, int context)
{
assert(address == makeLineAddress(address));
- int64 cacheSet = addressToCacheSet(address);
+ int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
}
bool
-CacheMemory::isBlockInvalid(int64 cache_set, int64 loc)
+CacheMemory::isBlockInvalid(int64_t cache_set, int64_t loc)
{
return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
}
bool
-CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc)
+CacheMemory::isBlockNotBusy(int64_t cache_set, int64_t loc)
{
return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
}
Cycles getTagLatency() const { return tagArray.getLatency(); }
Cycles getDataLatency() const { return dataArray.getLatency(); }
- bool isBlockInvalid(int64 cache_set, int64 loc);
- bool isBlockNotBusy(int64 cache_set, int64 loc);
+ bool isBlockInvalid(int64_t cache_set, int64_t loc);
+ bool isBlockNotBusy(int64_t cache_set, int64_t loc);
// Hook for checkpointing the contents of the cache
void recordCacheContents(int cntrl, CacheRecorder* tr) const;
private:
// convert a Address to its location in the cache
- int64 addressToCacheSet(Addr address) const;
+ int64_t addressToCacheSet(Addr address) const;
// Given a cache tag: returns the index of the tag in a set.
// returns -1 if the tag is not found.
- int findTagInSet(int64 line, Addr tag) const;
- int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const;
+ int findTagInSet(int64_t line, Addr tag) const;
+ int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
// Private copy constructor and assignment operator
CacheMemory(const CacheMemory& obj);
RubyMemoryControl::init()
{
m_msg_counter = 0;
- assert(m_tFaw <= 62); // must fit in a uint64 shift register
+ assert(m_tFaw <= 62); // must fit in a uint64_t shift register
m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel;
m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel;
// m_tfaw_count keeps track of how many 1 bits are set
// in each shift register. When m_tfaw_count is >= 4,
// new activates are not allowed.
- m_tfaw_shift = new uint64[m_total_ranks];
+ m_tfaw_shift = new uint64_t[m_total_ranks];
m_tfaw_count = new int[m_total_ranks];
for (int i = 0; i < m_total_ranks; i++) {
m_tfaw_shift[i] = 0;
{
m_msg_counter = 0;
- assert(m_tFaw <= 62); // must fit in a uint64 shift register
+ assert(m_tFaw <= 62); // must fit in a uint64_t shift register
m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel;
m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel;
// Each entry indicates number of address-bus cycles until bank
// is reschedulable:
- int* m_bankBusyCounter;
- int* m_oldRequest;
+ int *m_bankBusyCounter;
+ int *m_oldRequest;
- uint64* m_tfaw_shift;
- int* m_tfaw_count;
+ uint64_t *m_tfaw_shift;
+ int *m_tfaw_count;
// Each of these indicates number of address-bus cycles until
// we can issue a new request of the corresponding type:
int m_ageCounter; // age of old requests; to detect starvation
int m_idleCount; // watchdog timer for shutting down
- MemCntrlProfiler* m_profiler_ptr;
+ MemCntrlProfiler *m_profiler_ptr;
class MemCntrlEvent : public Event
{
public:
- MemCntrlEvent(RubyMemoryControl* _mem_cntrl)
+ MemCntrlEvent(RubyMemoryControl *_mem_cntrl)
{
mem_cntrl = _mem_cntrl;
}
m_records.push_back(rec);
}
-uint64
-CacheRecorder::aggregateRecords(uint8_t** buf, uint64 total_size)
+uint64_t
+CacheRecorder::aggregateRecords(uint8_t **buf, uint64_t total_size)
{
std::sort(m_records.begin(), m_records.end(), compareTraceRecords);
int size = m_records.size();
- uint64 current_size = 0;
+ uint64_t current_size = 0;
int record_size = sizeof(TraceRecord) + m_block_size_bytes;
for (int i = 0; i < size; ++i) {
void addRecord(int cntrl, Addr data_addr, Addr pc_addr,
RubyRequestType type, Tick time, DataBlock& data);
- uint64 aggregateRecords(uint8_t** data, uint64 size);
+ uint64_t aggregateRecords(uint8_t **data, uint64_t size);
/*!
* Function for flushing the memory contents of the caches to the
void
RubySystem::makeCacheRecorder(uint8_t *uncompressed_trace,
- uint64 cache_trace_size,
- uint64 block_size_bytes)
+ uint64_t cache_trace_size,
+ uint64_t block_size_bytes)
{
vector<Sequencer*> sequencer_map;
Sequencer* sequencer_ptr = NULL;
void
RubySystem::writeCompressedTrace(uint8_t *raw_data, string filename,
- uint64 uncompressed_trace_size)
+ uint64_t uncompressed_trace_size)
{
// Create the checkpoint file for the memory
string thefile = CheckpointIn::dir() + "/" + filename.c_str();
// Store the cache-block size, so we are able to restore on systems with a
// different cache-block size. CacheRecorder depends on the correct
// cache-block size upon unserializing.
- uint64 block_size_bytes = getBlockSizeBytes();
+ uint64_t block_size_bytes = getBlockSizeBytes();
SERIALIZE_SCALAR(block_size_bytes);
// Check that there's a valid trace to use. If not, then memory won't be
// Aggregate the trace entries together into a single array
uint8_t *raw_data = new uint8_t[4096];
- uint64 cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data,
+ uint64_t cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data,
4096);
string cache_trace_file = name() + ".cache.gz";
writeCompressedTrace(raw_data, cache_trace_file, cache_trace_size);
void
RubySystem::readCompressedTrace(string filename, uint8_t *&raw_data,
- uint64& uncompressed_trace_size)
+ uint64_t &uncompressed_trace_size)
{
// Read the trace file
gzFile compressedTrace;
// This value should be set to the checkpoint-system's block-size.
// Optional, as checkpoints without it can be run if the
// checkpoint-system's block-size == current block-size.
- uint64 block_size_bytes = getBlockSizeBytes();
+ uint64_t block_size_bytes = getBlockSizeBytes();
UNSERIALIZE_OPT_SCALAR(block_size_bytes);
string cache_trace_file;
- uint64 cache_trace_size = 0;
+ uint64_t cache_trace_size = 0;
UNSERIALIZE_SCALAR(cache_trace_file);
UNSERIALIZE_SCALAR(cache_trace_size);
RubySystem& operator=(const RubySystem& obj);
void makeCacheRecorder(uint8_t *uncompressed_trace,
- uint64 cache_trace_size,
- uint64 block_size_bytes);
+ uint64_t cache_trace_size,
+ uint64_t block_size_bytes);
void readCompressedTrace(std::string filename,
uint8_t *&raw_data,
- uint64& uncompressed_trace_size);
+ uint64_t &uncompressed_trace_size);
void writeCompressedTrace(uint8_t *raw_data, std::string file,
- uint64 uncompressed_trace_size);
+ uint64_t uncompressed_trace_size);
private:
// configuration parameters
void countTransition(${ident}_State state, ${ident}_Event event);
void possibleTransition(${ident}_State state, ${ident}_Event event);
- uint64 getEventCount(${ident}_Event event);
+ uint64_t getEventCount(${ident}_Event event);
bool isPossible(${ident}_State state, ${ident}_Event event);
- uint64 getTransitionCount(${ident}_State state, ${ident}_Event event);
+ uint64_t getTransitionCount(${ident}_State state, ${ident}_Event event);
private:
''')
m_possible[state][event] = true;
}
-uint64
+uint64_t
$c_ident::getEventCount(${ident}_Event event)
{
return m_event_counters[event];
return m_possible[state][event];
}
-uint64
+uint64_t
$c_ident::getTransitionCount(${ident}_State state,
${ident}_Event event)
{
projects / gem5.git / commitdiff