make sure that page bits of VA on tlb insert are 0

--HG--
extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 460a9c640c17a588c6ca4f488f12afc97f108634..61445954fc22fdc703d3a0907ef46b074be15fab 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -85,6 +85,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
     int x;
 
     cacheValid = false;
+    va &= ~(PTE.size()-1);
  /*   tr.va = va;
     tr.size = PTE.size() - 1;
     tr.contextId = context_id;