--- /dev/null
+// -*- mode:c++ -*-
+// Copyright (c) 2018 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Giacomo Travaglini
+
+//
+// A new class of Semihosting constructor templates has been added.
+// Their main purpose is to check if the Exception Generation
+// Instructions (HLT, SVC) are actually a semihosting command.
+// If that is the case, the IsMemBarrier flag is raised, so that
+// in the O3 model we perform a coherent memory access during
+// the semihosting operation.
+// Please note: since we don't have a thread context pointer in the
+// constructor we cannot check if semihosting is enabled in the
+// system. This is not affecting functional correctness, it just
+// means O3 models will flush the LSQ even if semihosting is disabled
+// when a semihosting immediate is recognized.
+
+def template SemihostConstructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
+ {
+ %(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
+
+ // In AArch32 semihosting commands can be issued by either
+ // SVC and HLT instructions. Another degree of freedom
+ // is added by the operating mode (Arm or Thumb)
+ auto semihost_imm = machInst.thumb? %(thumb_semihost)s :
+ %(arm_semihost)s;
+ if (_imm == semihost_imm) {
+ flags[IsMemBarrier] = true;
+ }
+ }
+}};
+
+def template SemihostConstructor64 {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
+ {
+ %(constructor)s;
+
+ // In AArch64 there is only one instruction for issuing
+ // semhosting commands: HLT #0xF000
+ if (_imm == 0xF000) {
+ flags[IsMemBarrier] = true;
+ }
+ }
+}};
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