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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 33ef7aad57f889843cc6e555707b7b7f2155b9e3..e0051edc1293f4a66ece716ce822251bfff3a4a0 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -21,10 +21,7 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
 |dz |VLi| 01    | inv |  CR-bit | normal mode      |
 |sz |VLi| 01    | inv |  dz Rc1 | VLSET mode       |
 
-Operations that actually produce or alter CR Field as a result do not
-also in turn have an Rc=1 mode.  However it makes no sense to try to test
-the 4 bits of a CR Field for being equal or not equal to zero. Moreover,
-the result is already in the form that is desired: it is a CR field.
+Fields:
 
 There are two primary different types of CR operations: