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lkcl
<lkcl@web>
Mon, 25 May 2020 21:50:06 +0000
(22:50 +0100)
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IkiWiki
<ikiwiki.info>
Mon, 25 May 2020 21:50:06 +0000
(22:50 +0100)
3d_gpu/architecture/compunit.mdwn
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diff --git
a/3d_gpu/architecture/compunit.mdwn
b/3d_gpu/architecture/compunit.mdwn
index 32cf65bc9287eb4a9d5343fa8cbdc3b4a5755539..b14020b16cd0f4c7f0d385fe87bda3ed9d991212 100644
(file)
--- a/
3d_gpu/architecture/compunit.mdwn
+++ b/
3d_gpu/architecture/compunit.mdwn
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-65,6
+65,8
@@
Note that the read and write latches are held synchronously for one cycle,
i.e. that when Go_Read comes in, one cycle is given in which the incoming
register (broadcast over a Regfile Read Port) may have time to be latched.
+It is REQUIRED that Issue be held valid only for one cycle.
+
It is REQUIRED that Go_Read be held valid only for one cycle, and it is
REQUIRED that the corresponding Read_Req be dropped exactly one cycle after
Go_Read is asserted HI.