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diff --git a/nlnet_2022_opf_isa_wg.mdwn b/nlnet_2022_opf_isa_wg.mdwn
index eeb170a20d622b074a64a37d35ec864ba64be51c..86dff2a6eda6ad56d8be7168e3a8cd06aa0d0b53 100644 (file)
--- a/nlnet_2022_opf_isa_wg.mdwn
+++ b/nlnet_2022_opf_isa_wg.mdwn
@@ -23,7 +23,8 @@ if you need any HTML to make your point please include this as attachment.
 The current NLnet funding to date has allowed Libre-SOC to develop
 one of the most powerful Scalable Vector ISAs in the world.
 The 25-year-old Power ISA, developed and curated by IBM, was
-transferred to the OpenPOWER Foundation, and is the basis of
+transferred to the OpenPOWER Foundation, and is the basis on
+which, with NLnet EU funding, we have based
 Simple-V, the Draft Scalable Vector Extension.
 
 Simple-V *needs* to be submitted to the OPF ISA Working Group,
@@ -32,12 +33,12 @@ pages we expect this to be done carefully and incrementally.
 https://ftp.libre-soc.org/simple_v_spec.pdf
 
 However the
-process of submitting Requests For Change, at the time of writing,
+process of submitting RFCs (Requests For Change), at the time of writing,
 still has not been publicly announced and opened up. We expect it
-to be very soon, but obviously could not begin any RFC Submission as
-part of the earlier NLnet funding.
+to be very soon, but obviously could not begin any RFC Submission
+as part of earlier NLnet funding.  The timing is now right.
 
-We will also become informed very shortly of the procedures but anticipate
+We will become publicly informed very shortly of the procedures but anticipate
 it to include development and submission of Compliance Test Suites
 (already partly covered by Simple-V unit tests, kindly funded by NLnet)
 as well as ongoing work on the Simulator.
@@ -45,10 +46,19 @@ as well as ongoing work on the Simulator.
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
 A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
-and includes the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
-the world's first in-place Discrete Cosine Transform algorithm;
-Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs) to do an 800,000 transistor fully automated RTL2GDSII
-tape-out; the side-benefits alone are enormous.
+and includes
+
+* the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
+* the world's first in-place Discrete Cosine Transform algorithm;
+* Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
+ to do an 800,000 transistor fully automated RTL2GDSII
+tape-out;
+* development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
+  ASIC ever taped-out in Europe (and funded by Horizon 2020)
+* development of an Interoperability "Test API" for Power ISA systems,
+  with thousands of unit tests.
+
+and much more. The side-benefits alone for EU citizens are enormous.
 
 # Requested Amount