add zero predication section

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 0cf5c2468243ea88af213fb1937c7c882431287e..44495301404cbb3d86b886d8b0dd57255ad407e1 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1893,6 +1893,8 @@ Therefore, looking purely at whether zeroing is *useful* or not,
 given that a case can be made for zeroing *and* non-zeroing, the
 decision was taken to add support for both.
 
+## Single-predication (based on destination register)
+
 Zeroing on predication for arithmetic operations is taken from
 the destination register's predicate.  i.e. the predication *and*
 zeroing settings to be applied to the whole operation come from the
@@ -1936,6 +1938,8 @@ circumstances it is perfectly fine to simply have the lanes
 "inactive" for predicated elements, even though it results in
 less than 100% ALU utilisation.
 
+## Twin-predication (based on source and destination register)
+
 Twin-predication is not that much different, except that that
 the source is independently zero-predicated from the destination.
 This means that the source may be zero-predicated *or* the