fhdl: allow a namespace to be specified for Verilog conversion

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 4c22fd4ce37ce7f2e5f1617f5af9d27bdff42c9d..219b71418809e20f433eac568530d6b69c3332ad 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -115,12 +115,12 @@ def _printinstances(ns, i, clk, rst):
                r += ");\n\n"
        return r
 
-def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst"):
-       ns = Namespace()
-       
+def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst", ns=None):
+       if ns is None: ns = Namespace()
+
        clks = Signal(name=clkname)
        rsts = Signal(name=rstname)
-       
+
        ios |= f.pads
 
        sigs = ListSignals(f)