ppc: support maddedus instruction
authorDmitry Selyutin <ghostmansd@gmail.com>
Sun, 28 May 2023 22:04:57 +0000 (01:04 +0300)
committerDmitry Selyutin <ghostmansd@gmail.com>
Tue, 14 Nov 2023 19:53:37 +0000 (22:53 +0300)
gas/testsuite/gas/ppc/maddedus.d [new file with mode: 0644]
gas/testsuite/gas/ppc/maddedus.s [new file with mode: 0644]
gas/testsuite/gas/ppc/ppc.exp
opcodes/ppc-opc.c

diff --git a/gas/testsuite/gas/ppc/maddedus.d b/gas/testsuite/gas/ppc/maddedus.d
new file mode 100644 (file)
index 0000000..994abfd
--- /dev/null
@@ -0,0 +1,12 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(13 e0 00 39|39 00 e0 13)\s+maddedus\s+r31,r0,r0,r0
+.*:\s+(10 1f 00 39|39 00 1f 10)\s+maddedus\s+r0,r31,r0,r0
+.*:\s+(10 00 f8 39|39 f8 00 10)\s+maddedus\s+r0,r0,r31,r0
+.*:\s+(10 00 07 f9|f9 07 00 10)\s+maddedus\s+r0,r0,r0,r31
diff --git a/gas/testsuite/gas/ppc/maddedus.s b/gas/testsuite/gas/ppc/maddedus.s
new file mode 100644 (file)
index 0000000..79a19f4
--- /dev/null
@@ -0,0 +1,4 @@
+maddedus 31,0,0,0
+maddedus 0,31,0,0
+maddedus 0,0,31,0
+maddedus 0,0,0,31
index cc4c755df1e8c6247d79911aa81a9d3f0cdf9df4..549e14158721673cd3c1e459c77028c05db40229 100644 (file)
@@ -173,3 +173,4 @@ run_dump_test "divmod2du"
 run_dump_test "sadd"
 run_dump_test "dsld"
 run_dump_test "dsrd"
+run_dump_test "maddedus"
index 96037806129cfa9b27b989389ae3b1f9b467ed81..a88e483866f60bc3d65f624c11ae36f6a70e23ce 100644 (file)
@@ -5261,6 +5261,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ps_mul.",    A  (4,  25,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
 {"maddedu",    VXA(4,  50),    VXA_MASK,    SFFS,      PPCVLE,         {RT, RA, RB, RC}},
 {"maddld",     VXA(4,  51),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
+{"maddedus",   VXA(4,  57),    VXA_MASK,    SFFS,      PPCVLE,         {RT, RA, RB, RC}},
 {"divmod2du",  VXA(4,  58),    VXA_MASK,    SFFS,      0,              {RT, RA, RB, RC}},
 {"ps_rsqrte",  A  (4,  26,0), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
 {"ps_rsqrte.", A  (4,  26,1), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},