from Device import PioDevice
simobj AlphaConsole(PioDevice):
+ type = 'AlphaConsole'
cpu = Param.BaseCPU(Super, "Processor")
disk = Param.SimpleDisk("Simple Disk")
- num_cpus = Param.Int(1, "Number of CPU's")
+ num_cpus = Param.Int(1, "Number of CPUs")
sim_console = Param.SimConsole(Super, "The Simulator Console")
system = Param.BaseSystem(Super, "system object")
simobj AlphaTLB(SimObject):
+ type = 'AlphaTLB'
abstract = True
size = Param.Int("TLB size")
simobj AlphaDTB(AlphaTLB):
+ type = 'AlphaDTB'
size = 64
simobj AlphaITB(AlphaTLB):
+ type = 'AlphaITB'
size = 48
from Device import PioDevice
simobj BadDevice(PioDevice):
+ type = 'BadDevice'
devicename = Param.String("Name of device to error on")
simobj BaseCPU(SimObject):
+ type = 'BaseCPU'
abstract = True
icache = Param.BaseMem(NULL, "L1 instruction cache object")
dcache = Param.BaseMem(NULL, "L1 data cache object")
from BaseMem import BaseMem
simobj BaseCache(BaseMem):
+ type = 'BaseCache'
adaptive_compression = Param.Bool(false,
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
simobj BaseSystem(SimObject):
+ type = 'BaseSystem'
abstract = True
memctrl = Param.MemoryController(Super, "memory controller")
physmem = Param.PhysicalMemory(Super, "phsyical memory")
from BaseHier import BaseHier
simobj Bus(BaseHier):
+ type = 'Bus'
clock_ratio = Param.Int("ratio of CPU to bus frequency")
width = Param.Int("bus width in bytes")
Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi')
simobj CoherenceProtocol(SimObject):
+ type = 'CoherenceProtocol'
do_upgrades = Param.Bool(true, "use upgrade transactions?")
protocol = Param.Coherence("name of coherence protocol")
# initialization phase at which point all SimObject pointers will be
# valid.
simobj FooPioDevice(FunctionalMemory):
- abstract = True
type = 'PioDevice'
+ abstract = True
addr = Param.Addr("Device Address")
mmu = Param.MemoryController(Super, "Memory Controller")
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
simobj FooDmaDevice(FooPioDevice):
- abstract = True
type = 'DmaDevice'
+ abstract = True
simobj PioDevice(FooPioDevice):
+ type = 'PioDevice'
abstract = True
platform = Param.Platform(Super, "Platform")
simobj DmaDevice(PioDevice):
+ type = 'DmaDevice'
abstract = True
simobj DiskImage(SimObject):
+ type = 'DiskImage'
abstract = True
image_file = Param.String("disk image file")
read_only = Param.Bool(false, "read only image")
simobj RawDiskImage(DiskImage):
- pass
+ type = 'RawDiskImage'
simobj CowDiskImage(DiskImage):
+ type = 'CowDiskImage'
child = Param.DiskImage("child image")
table_size = Param.Int(65536, "initial table size")
image_file = ''
from Pci import PciDevice
simobj EtherInt(SimObject):
+ type = 'EtherInt'
abstract = True
peer = Param.EtherInt(NULL, "peer interface")
simobj EtherLink(SimObject):
+ type = 'EtherLink'
int1 = Param.EtherInt("interface 1")
int2 = Param.EtherInt("interface 2")
delay = Param.Tick(0, "transmit delay of packets in us")
dump = Param.EtherDump(NULL, "dump object")
simobj EtherBus(SimObject):
+ type = 'EtherBus'
loopback = Param.Bool(true,
"send packet back to the interface from which it came")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.UInt64(100000000, "bus speed in bits per second")
simobj EtherTap(EtherInt):
+ type = 'EtherTap'
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
port = Param.UInt16(3500, "tap port")
simobj EtherDump(SimObject):
+ type = 'EtherDump'
file = Param.String("dump file")
simobj EtherDev(DmaDevice):
+ type = 'EtherDev'
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
tlaser = Param.Turbolaser(Super, "Turbolaser")
simobj NSGigE(PciDevice):
+ type = 'NSGigE'
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
physmem = Param.PhysicalMemory(Super, "Physical Memory")
simobj EtherDevInt(EtherInt):
+ type = 'EtherDevInt'
device = Param.EtherDev("Ethernet device of this interface")
simobj NSGigEInt(EtherInt):
+ type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")
IdeID = Enum('master', 'slave')
simobj IdeDisk(SimObject):
+ type = 'IdeDisk'
delay = Param.Tick(1, "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
physmem = Param.PhysicalMemory(Super, "Physical memory")
simobj IdeController(PciDevice):
+ type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
simobj IntrControl(SimObject):
+ type = 'IntrControl'
cpu = Param.BaseCPU(Super, "the cpu")
simobj MemTest(SimObject):
+ type = 'MemTest'
cache = Param.BaseCache("L1 cache")
check_mem = Param.FunctionalMemory("check memory")
main_mem = Param.FunctionalMemory("hierarchical memory")
from Device import FooPioDevice, DmaDevice
simobj PciConfigData(FooPioDevice):
+ type = 'PciConfigData'
addr = 0xffffffffffffffffL
VendorID = Param.UInt16("Vendor ID")
DeviceID = Param.UInt16("Device ID")
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
simobj PciConfigAll(FooPioDevice):
- pass
+ type = 'PciConfigAll'
simobj PciDevice(DmaDevice):
+ type = 'PciDevice'
abstract = True
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
from FunctionalMemory import FunctionalMemory
simobj PhysicalMemory(FunctionalMemory):
+ type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
mmu = Param.MemoryController(Super, "Memory Controller")
simobj Platform(SimObject):
+ type = 'Platform'
abstract = True
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
intrctrl = Param.IntrControl(Super, "interrupt controller")
simobj Process(SimObject):
+ type = 'Process'
abstract = True
output = Param.String('cout', 'filename for stdout/stderr')
simobj LiveProcess(Process):
+ type = 'LiveProcess'
cmd = VectorParam.String("command line (executable plus arguments)")
env = VectorParam.String('', "environment settings")
input = Param.String('cin', "filename for stdin")
simobj EioProcess(Process):
+ type = 'EioProcess'
chkpt = Param.String('', "EIO checkpoint file name (optional)")
file = Param.String("EIO trace file name")
simobj Repl(SimObject):
+ type = 'Repl'
abstract = True
simobj GenRepl(Repl):
+ type = 'GenRepl'
fresh_res = Param.Int("associativity")
num_pools = Param.Int("capacity in bytes")
pool_res = Param.Int("block size in bytes")
from HierParams import HierParams
simobj Root(SimObject):
+ type = 'Root'
frequency = Param.Tick(200000000, "tick frequency")
output_dir = Param.String('.', "directory to output data to")
output_file = Param.String('cout', "file to dump simulator output to")
simobj ConsoleListener(SimObject):
+ type = 'ConsoleListener'
port = Param.UInt16(3456, "listen port")
simobj SimConsole(SimObject):
+ type = 'SimConsole'
append_name = Param.Bool(true, "append name() to filename")
intr_control = Param.IntrControl(Super, "interrupt controller")
listener = Param.ConsoleListener("console listener")
number = Param.Int(0, "console number")
- output = Param.String("", "file to dump output to")
+ output = Param.String('', "file to dump output to")
simobj SimpleDisk(SimObject):
+ type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
physmem = Param.PhysicalMemory(Super, "Physical Memory")
from Platform import Platform
simobj Tsunami(Platform):
+ type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.BaseSystem(Super, "system")
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
+ type = 'TsunamiCChip'
tsunami = Param.Tsunami(Super, "Tsunami")
simobj TsunamiFake(FooPioDevice):
- pass
+ type = 'TsunamiFake'
simobj TsunamiIO(FooPioDevice):
+ type = 'TsunamiIO'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(Super, "Tsunami")
simobj TsunamiPChip(FooPioDevice):
+ type = 'TsunamiPChip'
tsunami = Param.Tsunami(Super, "Tsunami")
from Device import PioDevice
simobj Uart(PioDevice):
+ type = 'Uart'
console = Param.SimConsole(Super, "The console")
size = Param.Addr(0x8, "Device size")
import os, os.path, re
-def WriteEmbeddedPyFile(target, source, path, name, ext):
+def WriteEmbeddedPyFile(target, source, path, name, ext, filename):
if isinstance(source, str):
source = file(source, 'r')
if isinstance(target, str):
target = file(target, 'w')
- print >>target, "AddModule(%s, %s, %s, '''\\" % (`path`, `name`, `ext`)
+ print >>target, "AddModule(%s, %s, %s, %s, '''\\" % \
+ (`path`, `name`, `ext`, `filename`)
for line in source:
line = line
name,ext = pyfile.split('.')
if name == '__init__':
node['.hasinit'] = True
- node[pyfile] = (src,name,ext)
+ node[pyfile] = (src,name,ext,src)
done = False
while not done:
raise NameError, 'package directory missing __init__.py'
populate(entry, path + [ name ])
else:
- pyfile,name,ext = entry
- files.append((pyfile, path, name, ext))
+ pyfile,name,ext,filename = entry
+ files.append((pyfile, path, name, ext, filename))
populate(tree)
- for pyfile, path, name, ext in files:
- WriteEmbeddedPyFile(target, pyfile, path, name, ext)
+ for pyfile, path, name, ext, filename in files:
+ WriteEmbeddedPyFile(target, pyfile, path, name, ext, filename)
CFileCounter = 0
def MakePythonCFile(target, source, env):
return False
+class_decorator = '_M5M5_SIMOBJECT_'
+expr_decorator = '_M5M5_EXPRESSION_'
+dot_decorator = '_M5M5_DOT_'
+
# The metaclass for ConfigNode (and thus for everything that derives
# from ConfigNode, including SimObject). This class controls how new
# classes that derive from ConfigNode are instantiated, and provides
class MetaConfigNode(type):
keywords = { 'abstract' : types.BooleanType,
'check' : types.FunctionType,
- '_init' : types.FunctionType,
'type' : (types.NoneType, types.StringType) }
# __new__ is called before __init__, and is where the statements
'_disable' : {} }
for key,val in dict.items():
+ del dict[key]
+
+ if key.startswith(expr_decorator):
+ key = key[len(expr_decorator):]
+
if mcls.keywords.has_key(key):
if not isinstance(val, mcls.keywords[key]):
raise TypeError, \
if isinstance(val, types.FunctionType):
val = classmethod(val)
priv[key] = val
- del dict[key]
elif key.startswith('_'):
priv[key] = val
- del dict[key]
elif not isNullPointer(val) and isConfigNode(val):
dict[key] = val()
elif isSimObjSequence(val):
dict[key] = [ v() for v in val ]
+ else:
+ dict[key] = val
+
# If your parent has a value in it that's a config node, clone it.
for base in bases:
if not isConfigNode(base):
continue
- for name,value in base._values.iteritems():
- if dict.has_key(name):
+ for key,value in base._values.iteritems():
+ if dict.has_key(key):
continue
if isConfigNode(value):
- priv['_values'][name] = value()
+ priv['_values'][key] = value()
elif isSimObjSequence(value):
- priv['_values'][name] = [ val() for val in value ]
+ priv['_values'][key] = [ val() for val in value ]
# entries left in dict will get passed to __init__, where we'll
# deal with them as params.
cls._bases = [c for c in cls.__mro__ if isConfigNode(c)]
# initialize attributes with values from class definition
- for pname,value in dict.iteritems():
- setattr(cls, pname, value)
-
- if hasattr(cls, '_init'):
- cls._init()
- del cls._init
+ for key,value in dict.iteritems():
+ key = key.split(dot_decorator)
+ c = cls
+ for item in key[:-1]:
+ c = getattr(c, item)
+ setattr(c, key[-1], value)
def _isvalue(cls, name):
for c in cls._bases:
raise AttributeError, \
"object '%s' has no attribute '%s'" % (cls.__name__, cls)
-
# Set attribute (called on foo.attr = value when foo is an
# instance of class cls).
def __setattr__(cls, attr, value):
sys.path.append('../configs/kernel')
sys.path.append('../sim/pyconfig')
-from importer import mpy_exec, AddToPath
+from importer import mpy_exec, mpy_execfile, AddToPath
from m5config import *
try:
for arg in args:
AddToPath(os.path.dirname(arg))
- mpy_exec(file(arg, 'r'), globals())
+ mpy_execfile(arg)
if globals().has_key('root') and isinstance(root, type) \
and issubclass(root, Root):
projects / gem5.git / commitdiff