exponent bitwidth in DOUBLE2SINGLE needs to be 11 bits not 12

diff --git a/openpower/isafunctions/double2single.mdwn b/openpower/isafunctions/double2single.mdwn
index c9658057bcf2f6c6f5d4bd3d0c6126527a254d54..218beecd6006aea2b4b48d765328b6c3100441cf 100644 (file)
--- a/openpower/isafunctions/double2single.mdwn
+++ b/openpower/isafunctions/double2single.mdwn
@@ -32,7 +32,7 @@ Round to Single-Precision instruction.
         carry_out  <- tmp[24]
         frac[0:23] <- tmp[1:24]
         if carry_out = 1 then
-            exp[0:11] <- exp + 1
+            exp[0:10] <- exp + 1
             frac[0:23] <- 0b1 || frac[0:22]
         frac[24:52] <- [0]*29
         # TODO, later
@@ -66,7 +66,7 @@ Round to Single-Precision instruction.
                 mode <- 'snan_operand'
 
         frac <- [0]*53
-        exp <- [0]*12
+        exp <- [0]*11
         result <- [0] * 64
 
         if mode = 'normal_operand' then

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index a5e16b6baa13f54162ccb78d8038674265743a2f..6285a6690367e076d6268e3fe2f53b8e5b0180bd 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -215,7 +215,7 @@ class DecoderTestCase(FHDLTestCase):
         """>>> lst = ["fmuls 3, 1, 2",
                      ]
         """
-        lst = ["fmuls 3, 1, 2", # 
+        lst = ["fmuls 3, 1, 2", #
                      ]
 
         fprs = [0] * 32
@@ -226,6 +226,21 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_fprs=fprs)
             self.assertEqual(sim.fpr(3), SelectableInt(0x3d9b72ea40000000, 64))
 
+    def test_fp_muls3(self):
+        """>>> lst = ["fmuls 3, 1, 2",
+                     ]
+        """
+        lst = ["fmuls 3, 1, 2", #
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0xbfb0ab5100000000
+        fprs[2] = 0xbdca000000000000
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(3), SelectableInt(0x3d9d8b31c0000000, 64))
+
     def test_fp_mul(self):
         """>>> lst = ["fmul 3, 1, 2",
                      ]