Emit a flush after the swapbuffers blit, so contents end up on the screen.

Otherwise, since the MI_FLUSH at the end of every batch had been removed,
non-automatic-flushing chips (965) wouldn't get flushed and apps with static
rendering would get partial screen contents until the server's blockhandler
flush kicked in.

diff --git a/src/mesa/drivers/dri/i915/i830_reg.h b/src/mesa/drivers/dri/i915/i830_reg.h
index 41280bca7ce3504caf7c7407c7cf677f6a0094e3..d1084a84c0748f4a00e1b8ecdb13c5cceeecfc31 100644 (file)
--- a/src/mesa/drivers/dri/i915/i830_reg.h
+++ b/src/mesa/drivers/dri/i915/i830_reg.h
@@ -635,8 +635,4 @@
 #define ENABLE_TEX_STREAM_MAP_IDX      (1<<3)
 #define TEX_STREAM_MAP_IDX(x)          (x)
 
-
-#define MI_FLUSH           ((0<<29)|(4<<23))
-#define FLUSH_MAP_CACHE    (1<<0)
-
 #endif

diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index b5585e70e799f2f0737309dd3b5669624bd77ed7..b718b8610c77901f6dc1ea5f3a26b71c03e51675 100644 (file)
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -855,10 +855,4 @@
 #define _3DSTATE_DEFAULT_DIFFUSE    ((0x3<<29)|(0x1d<<24)|(0x99<<16))
 #define _3DSTATE_DEFAULT_SPECULAR   ((0x3<<29)|(0x1d<<24)|(0x9a<<16))
 
-
-#define MI_FLUSH                   ((0<<29)|(4<<23))
-#define FLUSH_MAP_CACHE            (1<<0)
-#define INHIBIT_FLUSH_RENDER_CACHE (1<<2)
-
-
 #endif

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3aada8cab1a36dad5137fb8c5b682a618d81365d..0fb531b1eebdd058f6084a02bc7bde63d8b22e38 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -38,7 +38,6 @@
 #define MI_NOOP                              0x00
 #define MI_USER_INTERRUPT                    0x02
 #define MI_WAIT_FOR_EVENT                    0x03
-#define MI_FLUSH                             0x04
 #define MI_REPORT_HEAD                       0x07
 #define MI_ARB_ON_OFF                        0x08
 #define MI_BATCH_BUFFER_END                  0x0A

diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 3d7f64e28bbe09ef7448dda788c6679c6203f53f..a1f499731262ee2be8df42b455525807475a66b5 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -159,6 +159,14 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
         ADVANCE_BATCH();
       }
 
+      /* Emit a flush so that, on systems where we don't have automatic flushing
+       * set (such as 965), the results all land on the screen in a timely
+       * fashion.
+       */
+      BEGIN_BATCH(1, IGNORE_CLIPRECTS);
+      OUT_BATCH(MI_FLUSH);
+      ADVANCE_BATCH();
+
       intel_batchbuffer_flush(intel->batch);
    }
 

diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index 37629c07e2f74b6c5dad15aec363763cd942e61f..c12ccf4ae1826e80ac24735e3eb846321f55d41c 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -31,6 +31,10 @@
 
 #define MI_BATCH_BUFFER_END            (CMD_MI | 0xA << 23)
 
+#define MI_FLUSH                       (CMD_MI | (4 << 23))
+#define FLUSH_MAP_CACHE                                (1 << 0)
+#define INHIBIT_FLUSH_RENDER_CACHE             (1 << 2)
+
 /* Stalls command execution waiting for the given events to have occurred. */
 #define MI_WAIT_FOR_EVENT               (CMD_MI | (0x3 << 23))
 #define MI_WAIT_FOR_PLANE_B_FLIP        (1<<6)