soc/integration/builder: pass output_dir to platform, make sure gateware/software...

diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py
index 0e6a38bc502c66c1e400a9fa052fac8d1d11915f..772f77a1e89658defa20b281b9a6705d96b1ed57 100644 (file)
--- a/litex/build/generic_platform.py
+++ b/litex/build/generic_platform.py
@@ -268,6 +268,7 @@ class GenericPlatform:
         self.name = name
         self.sources = []
         self.verilog_include_paths = []
+        self.output_dir = None
         self.finalized = False
 
     def request(self, *args, **kwargs):

diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index b6303a36545c5e51f6277371e7ed204de3d9c1e6..4b4eca60423c34afaaf3be6e43e00b7b2c5e6ace 100644 (file)
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -160,9 +160,11 @@ class Builder:
         self.soc.initialize_rom(bios_data)
 
     def build(self, toolchain_path=None, **kwargs):
-        self.soc.finalize()
+        self.soc.platform.output_dir = self.output_dir
+        os.makedirs(os.path.join(self.output_dir, "gateware"), exist_ok=True)
+        os.makedirs(os.path.join(self.output_dir, "software"), exist_ok=True)
 
-        os.makedirs(self.output_dir, exist_ok=True)
+        self.soc.finalize()
 
         self._generate_includes()
         if self.soc.cpu_type is not None: