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diff --git a/3d_gpu/architecture/decoder.mdwn b/3d_gpu/architecture/decoder.mdwn
index 737b146196235c5992aded7e2b5719c9ea0f5f9b..e049ec9bef3c96ed9ab6edc14e5b695ef87e9709 100644 (file)
--- a/3d_gpu/architecture/decoder.mdwn
+++ b/3d_gpu/architecture/decoder.mdwn
@@ -1,5 +1,7 @@
 # Decoder
 
+<http://bugs.libre-riscv.org/show_bug.cgi?id=186>
+
 The decoder is in charge of translating the RISCV or POWER instruction stream into operations that can be handled by our backend. It will have an extra input bit, set via a MSR that will switch which architecture it treats an instruction as.
 
 Source code: <https://git.libre-riscv.org/?p=soc.git;a=tree;f=src/soc/decoder;hb=HEAD>