Fix initialisation of flops

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 4bb4058b1ec7cf31416dc5cb184cfc823f25c76d..51bea4d57a95a9355a12710d6725756e959b4b12 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -520,8 +520,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                continue;
                        }
                        else if (cell->type.in("$_FF_")) {
-                               SigBit D = cell->getPort("\\D");
-                               SigBit Q = cell->getPort("\\Q");
+                               RTLIL::Wire *D = cell->getPort("\\D").as_wire();
+                               RTLIL::Wire *Q = cell->getPort("\\Q").as_wire();
+                               Q->attributes.swap(D->attributes);
                                module->connect(Q, D);
                                it = module->cells_.erase(it);
                                continue;

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 8688c1c3b9f14327b24e687598c69946ec9df613..1f0635614eda94f98f0336c1b9ed2e039365948e 100644 (file)
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -28,7 +28,7 @@ module  \$_DFF_P_   (input D, C, output Q);
        FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
 `else
     wire Q_next;
-       \$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
+       \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
        \$_FF_ abc_dff (.D(Q_next), .Q(Q));
 `endif
 endmodule

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 375ab7af12c57eea2688299d5ccb14dcb1d32ec2..db43e13c195be128684444a0a701ac7d6fc31e63 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -275,9 +275,10 @@ struct SynthXilinxPass : public ScriptPass
                }
 
                if (check_label("map_cells")) {
-                       run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
                        if (abc == "abc9")
-                               run("techmap -D _ABC -map +/xilinx/ff_map.v t:$_DFF*");
+                               run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -D _ABC -map +/xilinx/ff_map.v");
+                       else
+                               run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
                        run("clean");
                }
 
@@ -286,23 +287,22 @@ struct SynthXilinxPass : public ScriptPass
                                run("read_verilog -icells -lib +/xilinx/abc_ff.v");
                                run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
                        }
-                       else if (help_mode) {
+                       else if (help_mode)
                                run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
-                               run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-                                               "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-                       }
-                       else {
+                       else
                                run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
-                               run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-                                               "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-                       }
                        run("clean");
 
                        // This shregmap call infers fixed length shift registers after abc
                        //   has performed any necessary retiming
                        if (!nosrl || help_mode)
                                run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-                       run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+                       if (abc == "abc9")
+                               run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+                       else
+                               run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+                       run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+                                       "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
                        run("clean");
                }