litex: get verilator simulation working and add sim target as example

diff --git a/MANIFEST.in b/MANIFEST.in
index 701237de3f8a8da1ca8a4e6ba5a9f96cc3a16202..e0d2604971d23245abca5f58e8b39bf7d1d7e1a9 100644 (file)
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1,3 +1,4 @@
+graft litex/build/sim
 graft litex/soc/software
 graft litex/soc/cores/cpu/lm32/verilog
 graft litex/soc/cores/cpu/mor1kx/verilog

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
new file mode 100644 (file)
index 0000000..5cd9d56
--- /dev/null
+++ b/litex/boards/targets/sim.py
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+
+import argparse
+import importlib
+
+from litex.gen import *
+from litex.boards.platforms import sim
+from litex.gen.genlib.io import CRG
+
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+from litex.soc.cores import uart
+
+
+class BaseSoC(SoCCore):
+    def __init__(self, **kwargs):
+        platform = sim.Platform()
+        SoCCore.__init__(self, platform,
+            clk_freq=int((1/(platform.default_clk_period))*1000000000),
+            integrated_rom_size=0x8000,
+            integrated_main_ram_size=16*1024,
+            with_uart=False,
+            **kwargs)
+        self.submodules.crg = CRG(platform.request(platform.default_clk_name))
+
+        self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
+        self.submodules.uart = uart.UART(self.uart_phy)
+
+
+def main():
+    parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(**soc_core_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build()
+
+
+if __name__ == "__main__":
+    main()

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 658392d7dabff98b3c46c332af7e9ae9cb645c06..fb8e87102a84e34b19a1dec614e9aadb526d3554 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -9,6 +9,9 @@ from litex.build import tools
 from litex.build.generic_platform import *
 
 
+sim_directory = os.path.abspath(os.path.dirname(__file__))
+
+
 def _build_tb(platform, vns, serial, template):
     def io_name(resource, subsignal=None):
         res = platform.lookup_request(resource)
@@ -81,7 +84,7 @@ def _build_tb(platform, vns, serial, template):
     tools.write_to_file("dut_tb.cpp", content)
 
 
-def _build_sim(platform, vns, build_name, include_paths, sim_path, serial, verbose):
+def _build_sim(platform, vns, build_name, include_paths, serial, verbose):
     include = ""
     for path in include_paths:
         include += "-I"+path+" "
@@ -97,7 +100,7 @@ make -j -C obj_dir/ -f Vdut.mk Vdut
     build_script_file = "build_" + build_name + ".sh"
     tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
 
-    _build_tb(platform, vns, serial, os.path.join("..", sim_path, "dut_tb.cpp"))
+    _build_tb(platform, vns, serial, os.path.join(sim_directory, "dut_tb.cpp"))
     if verbose:
         r = subprocess.call(["bash", build_script_file])
     else:
@@ -117,10 +120,8 @@ def _run_sim(build_name):
 
 
 class SimVerilatorToolchain:
-    # XXX fir sim_path
     def build(self, platform, fragment, build_dir="build", build_name="top",
-            sim_path="../migen/migen/build/sim/", serial="console",
-            run=True, verbose=False):
+            serial="console", run=True, verbose=False):
         tools.mkdir_noerror(build_dir)
         os.chdir(build_dir)
 
@@ -138,7 +139,7 @@ class SimVerilatorToolchain:
             if path not in include_paths:
                 include_paths.append(path)
         include_paths += platform.verilog_include_paths
-        _build_sim(platform, v_output.ns, build_name, include_paths, sim_path, serial, verbose)
+        _build_sim(platform, v_output.ns, build_name, include_paths, serial, verbose)
 
         if run:
             _run_sim(build_name)

diff --git a/litex/soc/cores/uart/__init__.py b/litex/soc/cores/uart/__init__.py
index 94097056716f31aed5beb250b90ad1ef049b8569..848ae4195995c4f97339264244415c8f114511eb 100644 (file)
--- a/litex/soc/cores/uart/__init__.py
+++ b/litex/soc/cores/uart/__init__.py
@@ -1 +1 @@
-from litex.soc.cores.uart.core import UART, RS232PHY
+from litex.soc.cores.uart.core import UART, RS232PHY, RS232PHYModel

diff --git a/litex/soc/cores/uart/core.py b/litex/soc/cores/uart/core.py
index ad283ef092e8ee6135d3a4db7ac73245bde70085..d394f5aa7702de64b1bb3fd618a91e4c9e912507 100644 (file)
--- a/litex/soc/cores/uart/core.py
+++ b/litex/soc/cores/uart/core.py
@@ -111,6 +111,22 @@ class RS232PHY(Module, AutoCSR):
         self.sink, self.source = self.tx.sink, self.rx.source
 
 
+class RS232PHYModel(Module):
+    def __init__(self, pads):
+        self.sink = Sink([("data", 8)])
+        self.source = Source([("data", 8)])
+
+        self.comb += [
+            pads.source_stb.eq(self.sink.stb),
+            pads.source_data.eq(self.sink.data),
+            self.sink.ack.eq(pads.source_ack),
+
+            self.source.stb.eq(pads.sink_stb),
+            self.source.data.eq(pads.sink_data),
+            pads.sink_ack.eq(self.source.ack)
+        ]
+
+
 def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
     if sink_cd != source_cd:
         fifo = AsyncFIFO([("data", 8)], depth)