added english language description for lwzsux instruction

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 7ace250ac863784ec2325857700aea490ad47c92..903019cd7094ffac1a385e31a72a0a15a8337d71 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -218,6 +218,19 @@ Pseudo-code:
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+
 Special Registers Altered:
 
     None