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diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 397afdc7a3435a303ba3952be7c7807943ed0749..275cb18243ff43b8bf6249d7bedd4aadbbac237b 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -120,7 +120,9 @@ mantissa may be achieved.
 v3.1 Prefixed (`pfmvis` and `pfishmv`). If so it is recommended that
 `pfmvis` load a full FP32 immediate and `pfishmv` supplies the three high
 missing exponent bits (numbered 8 to 10) and the lower additional
-29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.*
+29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.
+Strictly speaking the sequence `fmvis fishmv pfishmv` achieves the
+same effect in the same number of bytes, making `pfmvis` redundant.*
 
 ## Load BF16 Immediate
 
@@ -169,6 +171,12 @@ Pseudocode:
     fp32 = bf16 || [0]*16 # convert BF16 to FP32
     FRS = DOUBLE(fp32)    # convert FP32 to FP64
 
+Special registers altered:
+
+    None
+
+Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv
+
 ## Float Immediate Second-Half MV <a name="fishmv"></a>
 
 `fishmv FRS, D`
@@ -199,6 +207,15 @@ Pseudocode:
     fp32[16:31] <- d0 || d1 || d2    # replace LSB half
     FRS <- DOUBLE(fp32)              # convert back to FP64
 
+Special registers altered:
+
+    None
+
+Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv.
+As this instruction is specifically intended to work in conjunction with fmvis
+to provide additional accuracy, all bits in FRS other than those which
+would have been set by an fmvis instruction are deliberately ignored
+
 **This instruction performs a Read-Modify-Write.** *FRS is read, the additional
 16 bit immediate inserted, and the result also written to FRS*