Add new box to cells_sim.v

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b746ba4e500a87af4b7894b1213736eed929839c..cf36f5cfb96e4b7b4f2a13d1789a2c458a5b6def 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2, lib_whitebox *)
+(* lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
        parameter [15:0] LUT_INIT = 0;
        wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,11 +136,34 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
        assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+(* lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
        assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+       SB_CARRY carry (
+               .I0(A),
+               .I1(B),
+               .CI(CI),
+               .CO(CO)
+       );
+       SB_LUT4 #(
+               //         I0: 1010 1010 1010 1010
+               //         I1: 1100 1100 1100 1100
+               //         I2: 1111 0000 1111 0000
+               //         I3: 1111 1111 0000 0000
+               .LUT_INIT(16'b 0110_1001_1001_0110)
+       ) adder (
+               .I0(1'b0),
+               .I1(A),
+               .I2(B),
+               .I3(CI),
+               .O(O)
+       );
+endmodule
+
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (output `SB_DFF_REG, input C, D);