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diff --git a/nlnet_2023_simplev_riscv_binutils.mdwn b/nlnet_2023_simplev_riscv_binutils.mdwn
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+++ b/nlnet_2023_simplev_riscv_binutils.mdwn
@@ -20,17 +20,22 @@ Please be short and to the point in your answers; focus primarily on the what an
 
 ## Abstract: Can you explain the whole project and its expected outcome(s).
 
-This project is to enhance binutils tools to support Simple-V capabilities for the RISC-V ISA. It will directly support the ISA Expansion project
+This project is to enhance binutils tools to continue the autogenerated supportfor the
+RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities.
+It will directly support the ISA Expansion project
 <https://libre-soc.org/nlnet_2023_simplev_riscv>
 for which a separate grant application has been made, and will build on learnings from
-binutils developed for POWER ISA. The outcome of the project will be the completion of binutil tools capable of creating and managing binary program files, including handling object files, libraries, profile data, and assembly source code.
+binutils developed for POWER ISA and SVP64/Power. The outcome of the project will be the completion of binutil tools capable of creating and managing binary program files, including handling object files, libraries, profile data, and assembly source code, as well as
+providing a machine-readable database and associated library for other projects to
+manipulate supported Instruction sets.
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
-A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of POWER. A full project list is maintained at: https://libre-soc.org/nlnet_proposals/ they include recently:
+A sequence of projects enabled early development (four years ago, 2019-03-012) 
+of vectorisation techniques in the RISC-V domain, and later higher performance
+demonstration with OpenPOWER ISA (2022-08-051). A full project list is maintained at: https://libre-soc.org/nlnet_proposals/ they include recently:
 
 * https://libre-soc.org/nlnet_2022_opf_isa_wg/ - improving SVP64 and submitting it to the OpenPOWER ISA Technical Working Group.
-
 * https://libre-soc.org/nlnet_2021_crypto_router/ - proving, improving, and demonstrating that SVP64 is capable of handling cryptographic primitives in an extreme power-efficient compact way as the basis for higher security products
 
 # Requested Amount