Added "read_verilog -dump_rtlil"

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 82b4edef16aa6a19ed37a3a64eeb4860b4a21fd1..29795590ca1702b114c90115ba08ac49c2315572 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -44,7 +44,8 @@ namespace AST {
 
 // instanciate global variables (private API)
 namespace AST_INTERNAL {
-       bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
+       bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+       bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
        AstNode *current_ast, *current_ast_mod;
        std::map<std::string, AstNode*> current_scope;
        const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
@@ -175,7 +176,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
 
 // create new node (AstNode constructor)
 // (the optional child arguments make it easier to create AST trees)
-AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
+AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *child3)
 {
        static unsigned int hashidx_count = 123456789;
        hashidx_count = mkhash_xorshift(hashidx_count);
@@ -203,6 +204,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
                children.push_back(child1);
        if (child2)
                children.push_back(child2);
+       if (child3)
+               children.push_back(child3);
 }
 
 // create a (deep recursive) copy of a node
@@ -969,16 +972,25 @@ static AstModule* process_module(AstNode *ast, bool defer)
        current_module->icells = flag_icells;
        current_module->autowire = flag_autowire;
        current_module->fixup_ports();
+
+       if (flag_dump_rtlil) {
+               log("Dumping generated RTLIL:\n");
+               log_module(current_module);
+               log("--- END OF RTLIL DUMP ---\n");
+       }
+
        return current_module;
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
+               bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
 {
        current_ast = ast;
        flag_dump_ast1 = dump_ast1;
        flag_dump_ast2 = dump_ast2;
        flag_dump_vlog = dump_vlog;
+       flag_dump_rtlil = dump_rtlil;
        flag_nolatches = nolatches;
        flag_nomeminit = nomeminit;
        flag_nomem2reg = nomem2reg;
@@ -1023,9 +1035,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 
                        design->add(process_module(*it, defer));
                }
-               else if ((*it)->type == AST_PACKAGE){
+               else if ((*it)->type == AST_PACKAGE)
                        design->verilog_packages.push_back((*it)->clone());
-               }
                else
                        global_decls.push_back(*it);
        }

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 5310bcadb50bccf7849076b1021459e4fc3a9caf..530c11ba59d76484a085c53c2eeed5232e6b355f 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -187,7 +187,7 @@ namespace AST
                int linenum;
 
                // creating and deleting nodes
-               AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL);
+               AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL);
                AstNode *clone();
                void cloneInto(AstNode *other);
                void delete_children();
@@ -272,7 +272,8 @@ namespace AST
        };
 
        // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-       void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
+       void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
+                       bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
 
        // parametric modules are supported directly by the AST library
        // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
@@ -302,7 +303,8 @@ namespace AST
 namespace AST_INTERNAL
 {
        // internal state variables
-       extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
+       extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+       extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
        extern AST::AstNode *current_ast, *current_ast_mod;
        extern std::map<std::string, AST::AstNode*> current_scope;
        extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 87ea8c6ae27a6e4d24ef9ebb79b8372c936702cb..8ec347e89bc6a42701025cf00a1813e932f2f5fc 100644 (file)
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -75,6 +75,9 @@ struct VerilogFrontend : public Frontend {
                log("    -dump_vlog\n");
                log("        dump ast as Verilog code (after simplification)\n");
                log("\n");
+               log("    -dump_rtlil\n");
+               log("        dump generated RTLIL netlist\n");
+               log("\n");
                log("    -yydebug\n");
                log("        enable parser debug output\n");
                log("\n");
@@ -168,6 +171,7 @@ struct VerilogFrontend : public Frontend {
                bool flag_dump_ast1 = false;
                bool flag_dump_ast2 = false;
                bool flag_dump_vlog = false;
+               bool flag_dump_rtlil = false;
                bool flag_nolatches = false;
                bool flag_nomeminit = false;
                bool flag_nomem2reg = false;
@@ -216,6 +220,10 @@ struct VerilogFrontend : public Frontend {
                                flag_dump_vlog = true;
                                continue;
                        }
+                       if (arg == "-dump_rtlil") {
+                               flag_dump_rtlil = true;
+                               continue;
+                       }
                        if (arg == "-yydebug") {
                                frontend_verilog_yydebug = true;
                                continue;
@@ -342,7 +350,7 @@ struct VerilogFrontend : public Frontend {
                if (flag_nodpi)
                        error_on_dpi_function(current_ast);
 
-               AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
+               AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
 
                if (!flag_nopp)
                        delete lexin;

diff --git a/kernel/log.cc b/kernel/log.cc
index fe84184a57e8c6b49d2e3e35bf6ad5f62a263c82..12dc453dc82f3b6a9d3a43b44bb9b8b2588510b5 100644 (file)
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -427,6 +427,13 @@ const char *log_id(RTLIL::IdString str)
        return p+1;
 }
 
+void log_module(RTLIL::Module *module, std::string indent)
+{
+       std::stringstream buf;
+       ILANG_BACKEND::dump_module(buf, indent, module, module->design, false);
+       log("%s", buf.str().c_str());
+}
+
 void log_cell(RTLIL::Cell *cell, std::string indent)
 {
        std::stringstream buf;

diff --git a/kernel/log.h b/kernel/log.h
index 33e624dcba218aaf3fe6e364564bb551ec8811d9..f830655c10dcc5e57ae234ed478c8e32863d703d 100644 (file)
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -85,6 +85,7 @@ template<typename T> static inline const char *log_id(T *obj) {
        return log_id(obj->name);
 }
 
+void log_module(RTLIL::Module *module, std::string indent = "");
 void log_cell(RTLIL::Cell *cell, std::string indent = "");
 
 #ifndef NDEBUG