cores/gpio: use separate TSTriple for each bit.

This fixes per bit OE control.

diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py
index a2541072f7efa2007872e9b2a24d9824dfb360e4..fb2e356819f64ef71421fa2b208935b8b076451f 100644 (file)
--- a/litex/soc/cores/gpio.py
+++ b/litex/soc/cores/gpio.py
@@ -34,12 +34,19 @@ class GPIOInOut(Module):
 
 class GPIOTristate(Module, AutoCSR):
     def __init__(self, pads):
-        self._oe  = CSRStorage(len(pads))
-        self._in  = CSRStatus(len(pads))
-        self._out = CSRStorage(len(pads))
-
-        t = TSTriple(len(pads))
-        self.specials += t.get_tristate(pads)
-        self.comb += t.oe.eq(self._oe.storage)
-        self.comb += t.o.eq(self._out.storage)
-        self.specials += MultiReg(t.i, self._in.status)
+        nbits     = len(pads)
+        self._oe  = CSRStorage(nbits)
+        self._in  = CSRStatus(nbits)
+        self._out = CSRStorage(nbits)
+
+        # # #
+
+        _pads = Signal(nbits)
+        self.comb += _pads.eq(pads)
+
+        for i in range(nbits):
+            t = TSTriple()
+            self.specials += t.get_tristate(_pads[i])
+            self.comb += t.oe.eq(self._oe.storage[i])
+            self.comb += t.o.eq(self._out.storage[i])
+            self.specials += MultiReg(t.i, self._in.status[i])