Fix partsel expr bit width handling and add test case

Signed-off-by: Claire Wolf <claire@symbioticeda.com>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index be8b39e9f70dc44cbcadd83a2493d3b424d35962..91982e2a35994729e879e16df497ffa2bbdb9158 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -593,13 +593,15 @@ non_opt_range:
        } |
        '[' expr TOK_POS_INDEXED expr ']' {
                $$ = new AstNode(AST_RANGE);
-               $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
-               $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
+               AstNode *expr = new AstNode(AST_CONCAT, $2);
+               $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
+               $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
        } |
        '[' expr TOK_NEG_INDEXED expr ']' {
                $$ = new AstNode(AST_RANGE);
-               $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
-               $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
+               AstNode *expr = new AstNode(AST_CONCAT, $2);
+               $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
+               $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
        } |
        '[' expr ']' {
                $$ = new AstNode(AST_RANGE);

diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index 7461358ad50b4000a36d0f1085930e6287a9c821..83493fcb0ec7f4e8d79f322b2822a45de8ef30bf 100644 (file)
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -60,3 +60,7 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
+assign dout = din[a*b +: 2];
+endmodule