freedreno/ir3: lower phi webs to regs

nir's from_ssa pass is much better at avoiding inserting extra moves
than our logic is.  And lowering phi webs to regs just treats anything
involved in a phi web as an array of length=1.  Which with previous
array related fixes in RA/etc ends up working out quite well.  This cuts
down on extra instructions and also helps with register pressure.

Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 72e0f4fe288f5c5bd8e7d2cc57e5e3401879851d..4c37461292f24216427feb983e14be07960fea07 100644 (file)
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -194,6 +194,7 @@ compile_init(struct ir3_compiler *compiler,
         * in ir3_optimize_nir():
         */
        NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
+       NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
 
        if (fd_mesa_debug & FD_DBG_DISASM) {
                DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
@@ -907,8 +908,6 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
                return;
        }
 
-       compile_assert(ctx, alu->dest.dest.is_ssa);
-
        /* General case: We can just grab the one used channel per src. */
        for (int i = 0; i < info->num_inputs; i++) {
                unsigned chan = ffs(alu->dest.write_mask) - 1;