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Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
authorEddie Hung <eddie@fpgeh.com>
Mon, 25 May 2020 21:21:10 +0000 (14:21 -0700)
committerGitHub <noreply@github.com>
Mon, 25 May 2020 21:21:10 +0000 (14:21 -0700)
xilinx: tidy up cells_sim.v a little


Trivial merge