struct pipe_context *pipe;
struct cso_context *cso;
- struct pipe_blend_state blend;
+ struct pipe_blend_state blend_write_color, blend_keep_color;
struct pipe_depth_stencil_alpha_state depthstencil_keep;
struct pipe_depth_stencil_alpha_state depthstencil_write;
struct pipe_rasterizer_state rasterizer;
ctx->cso = cso;
/* disabled blending/masking */
- ctx->blend.rt[0].colormask = PIPE_MASK_RGBA;
+ ctx->blend_write_color.rt[0].colormask = PIPE_MASK_RGBA;
/* no-op depth/stencil/alpha */
ctx->depthstencil_write.depth.enabled = 1;
cso_save_vertex_buffers(ctx->cso);
/* set misc state we care about */
- cso_set_blend(ctx->cso, &ctx->blend);
+ if (writemask)
+ cso_set_blend(ctx->cso, &ctx->blend_write_color);
+ else
+ cso_set_blend(ctx->cso, &ctx->blend_keep_color);
+
cso_set_depth_stencil_alpha(ctx->cso,
dst_is_depth ? &ctx->depthstencil_write :
&ctx->depthstencil_keep);
cso_save_vertex_buffers(ctx->cso);
/* set misc state we care about */
- cso_set_blend(ctx->cso, &ctx->blend);
+ cso_set_blend(ctx->cso, &ctx->blend_write_color);
cso_set_depth_stencil_alpha(ctx->cso, &ctx->depthstencil_keep);
cso_set_rasterizer(ctx->cso, &ctx->rasterizer);
cso_set_vertex_elements(ctx->cso, 2, ctx->velem);
srcX0, srcY0, srcX1, srcY1,
srcDepthRb->surface->u.tex.first_layer,
dstDepthSurf, dstX0, dstY0, dstX1, dstY1,
- 0.0, pFilter, TGSI_WRITEMASK_XYZW);
+ 0.0, pFilter, 0);
}
else {
/* blitting depth and stencil separately */
srcX0, srcY0, srcX1, srcY1,
srcDepthRb->surface->u.tex.first_layer,
dstDepthSurf, dstX0, dstY0, dstX1, dstY1,
- 0.0, pFilter, TGSI_WRITEMASK_XYZW);
+ 0.0, pFilter, 0);
}
if (mask & GL_STENCIL_BUFFER_BIT) {