add BM2-Form to power_enums.py

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index f23ff1ddb93aac46e45325a3658c3f73bcfb0192..c3d9ed55a06e7c19e7ab9b171dc6aec3b02cb332 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -17,4 +17,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 # Vector bitmanip
 0110001110-,ALU,OP_CPROP,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cprop,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cprop,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,bmask,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index f15cb4998ae561e9f3b68837864e8180d15f9544..776c3ee930fa03ca70554d33904166717b4c492f 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -125,6 +125,7 @@ class Form(Enum):
     SVRM = 33  # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
     TLI = 34  # ternlogi
     XB = 35
+    BM2 = 36 # bmask
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/